Signal boost for shift register

Claim 2

In combination: two clock conductors; a first gating device having a control electrode and two controlled electrodes, the control electrode being connected to a first clock conductor; a first storage device connected to a first controlled electrode of the first gating device; a second gating device having a control electrode and two controlled electrodes, a first one of the controlled electrodes being connected to the first clock conductor, and the control electrode being connected to the first controlled electrode of the first gating device; and a first coupling device connected directly between the second clock conductor and the first controlled electrode of the first gating device.

Claim 3

A combination according to claim 1 further comprising: a second storage device connected to the second controlled electrode of the second gating device.

Claim 4

A combination according tO claim 2 further comprising: a third gating device having a control electrode and two controlled electrodes, the control electrode and a first one of the controlled electrodes being connected to the first clock conductor and the second controlled electrode being connected to the second controlled electrode of the second gating device.

Claim 5

A combination according to claim 2 further comprising: a second coupling device connected between the second clock conductor and the second controlled electrode of the second gating device.

Claim 6

An improved memory circuit including at least one clock conductor; means for transferring a binary data input signal to a first storage means, and gating means responsive to the first storage means for gating a corresponding binary data output signal, wherein the improvement comprises: means responsive to a clock signal for increasing the signal stored in the storage means by substantially a constant magnitude irrespective of the binary sense of the signal stored therein.

Claim 7

An improved memory circuit including at least one clock conductor; means for transferring a binary data input signal to a first storage means, and gating means responsive to the first storage means for gating a corresponding binary data output signal, wherein the improvement comprises: means responsive to a clock signal for increasing the signal stored in the storage means by substantially a constant magnitude irrespective of the binary sense of the signal stored therein.

Claim 8

A circuit according to claim 5 further comprising a second storage means responsive to the operation of the gating means for storing the data output signal.

Claim 9

A circuit according to claim 6 further comprising booster means responsive to the clock signal for increasing the data output signal by a substantial magnitude irrespective of the binary sense of the output signal.

Claim 10

A shift register comprising a series of memory stages, each comprising two inverter cells, each cell inverting a succession of output binary data signals from a preceding cell and transferring the inverted signals to a subsequent cell, the shift register responding to a two-phase clock signal applied to first and second Clock conductors for operating adjacent cells alternately to shift the inverted data signal from each cell to the next, each cell comprising: a. a first memory capacitor; b. a first FET having its gate connected to the first clock conductor, a first controlled electrode connected to the output signal from the preceding cell, and a second controlled electrode connected to the memory capacitor, so that the first FET connects the output signal from the preceding cell to the memory capacitor during each clock pulse of a first clock phi 1, and the memory capacitor is thereafter isolated from the preceding cell by the first FET until the next cycle of phi 1, the memory capacitor storing a charge representing the output signal from the preceding cell; c. a second FET having its gate connected to the second controlled electrode of the first FET so that the memory capacitor voltage is applied to that gate, the memory capacitor charge being either a voltage above the threshold voltage of the second FET if a binary 1 is being stored, or near 0 volts if a binary 0 is being stored. d. means, triggered by the phi 1 clock pulse and governed by the state of the second FET after phi 1, for providing an output data signal from the cell comprising the inversion of the input signal from the preceding cell, the output signal being connected to the first FET of the following cell during a second clock pulse phi 2; and e. a first booster capacitor connected between the second clock conductor and the second controlled electrode of the first FET so as to supplement the voltage applied by the first memory capacitor to the gate of the second FET during phi 2, the booster capacitor providing insufficient voltage to the gate to operate the second FET when the first capacitor is storing a 0, but enhancing the operation of the second FET by a fixed and constant amount when a 1 is being stored.

Claim 11

A shift register comprising a series of memory stages, each comprising two inverter cells, each cell inverting a succession of output binary data signals from a preceding cell and transferring the inverted signals to a subsequent cell, the shift register responding to a two-phase clock signal applied to first and second Clock conductors for operating adjacent cells alternately to shift the inverted data signal from each cell to the next, each cell comprising: a. a first memory capacitor; b. a first FET having its gate connected to the first clock conductor, a first controlled electrode connected to the output signal from the preceding cell, and a second controlled electrode connected to the memory capacitor, so that the first FET connects the output signal from the preceding cell to the memory capacitor during each clock pulse of a first clock phi 1, and the memory capacitor is thereafter isolated from the preceding cell by the first FET until the next cycle of phi 1, the memory capacitor storing a charge representing the output signal from the preceding cell; c. a second FET having its gate connected to the second controlled electrode of the first FET so that the memory capacitor voltage is applied to that gate, the memory capacitor charge being either a voltage above the threshold voltage of the second FET if a binary 1 is being stored, or near 0 volts if a binary 0 is being stored. d. means, triggered by the phi 1 clock pulse and governed by the state of the second FET after phi 1, for providing an output data signal from the cell comprising the inversion of the input signal from the preceding cell, the output signal being connected to the first FET of the following cell during a second clock pulse phi 2; and e. a first booster capacitor connected between the second clock conductor and the second controlled electrode of the first FET so as to supplement the voltage applied by the first memory capacitor to the gate of the second FET during phi 2, the booster capacitor providing insufficient voltage to the gate to operate the second FET when the first capacitor is storing a 0, but enhancing the operation of the second FET by a fixed and constant amount when a 1 is being stored.

Claim 12

A shift register as recited in claim 8, wherein the first memory capacitor comprises and the first booster capacitor comprises a discretely-formed integrated-circuit capacitor.

Claim 13

A shift register as recited in claim 8, wherein a first controlled electrode of the second FET is connected to the first clock conductor, and wherein the means (d) for providing the inverted output signal comprises: a second memory capacitor connected to the second controlled electrode of the second FET; and means for precharging the second memory capacitor to the 1 cell-output voltage only during the phi 1 clock pulse, regardless of the state of the second FET, so that the second memory capacitor discharges to the ground of the phi 1 clock conductor after the phi 1 clock pulse if the second FET is ON (the first memory capacitor is storing a 1) and remains charged until after phi 2 clock pulse if the second FET is OFF (the first memory capacitor is storing a binary 0), the second memory capacitor being connected to the first controlled electrode of the first FET of the following cell so as to provide the input signal to the following cell representing the inversion of the input to the cell in question.

Claim 14

A shift register as recited in claim 10, further comprising a second booster capacitor connected between the second clock conductor and the second controlled electrode of the second FET, for applying, during the phi 2 clock pulse, a supplemental voltage to the first memory capacitor of the following cell through the first FET of the following cell, the supplemental voltage being selected to augment the 1 charge if present on the second memory capacitor, but to substantially discharge through the second FET to the ground of the phi 1 clock conductor if the second memory capacitor is storing a zero.

Claim 15

A shift register as recited in claim 11, wherein the first and second memory capacitors are inTrinsic capacitances of an integrated-circuit and the first and second booster capacitors are discretely-formed, integrated-circuit capacitors.

Claim 16

A shift register as recited in claim 12, wherein the means for precharging the second memory capacitor comprises a third FET having its gate connected to the phi 1 clock conductor, its first controlled electrode connected to the first controlled electrode of the second FET and to the phi 1 clock conductor, and its second controlled electrode connected to the second controlled electrode of the second FET and to the second memory capacitor and the second booster capacitor, whereby the third FET operates during the phi 1 clock pulse to precharge the second memorY capacitor from the phi 1 clock voltage, while precluding discharge of the second memory capacitor through the third FET to the phi 1 clock ground after the phi 1 pulse.

Claim 19

In a data-processing system of the type wherein one of two voltages indicating the state of a binary data signal is stored on a memory capacitor which is later coupled, in response to clock signal, to the gate of a switching device of the type requiring a threshold gate voltage to turn ON, and wherein a first of the possible capacitor charges applies a gate voltage above the threshold voltage and the second possible charges applies approximately zero volts or a voltage well below the threshold voltage, the improvement which comprises: applying a booster voltage to the gate of the switching device in response to the clock signal, the booster voltage supplementing any voltage applied by the memory capacitor so as to augment by a fixed and constant amount the operation of the switching device when the capacitor is storing the first charge, but the booster voltage being well below that required to operate the switching device when the capacitor is storing the second charge.

Claim 20

In a data-processing system of the type wherein one of two voltages indicating the state of a binary data signal is stored on a memory capacitor which is later coupled, in response to clock signal, to the gate of a switching device of the type requiring a threshold gate voltage to turn ON, and wherein a first of the possible capacitor charges applies a gate voltage above the threshold voltage and the second possible charges applies approximately zero volts or a voltage well below the threshold voltage, the improvement which comprises: applying a booster voltage to the gate of the switching device in response to the clock signal, the booster voltage supplementing any voltage applied by the memory capacitor so as to augment by a fixed and constant amount the operation of the switching device when the capacitor is storing the first charge, but the booster voltage being well below that required to operate the switching device when the capacitor is storing the second charge.

Claim 21

An improved inverter circuit comprising: first clock means for generating clock pulses; a first storage means for storing information; means responsive to the first clock means for preparing the storage means and removing any information stored therein; a source of data input signals; means responsive to the data input signals for selectively adjusting the storage means and thereby storing information therein; second clock means for generating second clock pulses alternating with the clock pulses generated by the first clock means; and means responsive to the second clock pulses for boosting the contents of the first storage means by a fixed and constant amount irrespective of the nature of the data signals.

Claim 22

An improved inverter circuit comprising: first clock means for generating clock pulses; a first storage means for storing information; means responsive to the first clock means for preparing the storage means and removing any information stored therein; a source of data input signals; means responsive to the data input signals for selectively adjusting the storage means and thereby storing information therein; second clock means for generating second clock pulses alternating with the clock pulses generated by the first clock means; and means responsive to the second clock pulses for boosting the contents of the first storage means by a fixed and constant amount irrespective of the nature of the data signals.

Claim 23

An inverter according to claim 16 wherein the boosting means comprises a second storage means connected between the first storage means and the second clock means.

Claim 24

In combination: two clock conductors; a first gating device having a control electrode and two controlled electrodes, the control electrode being connected to a first clock conductor; a first storage device connected to a first controlled electrode of the first gating device; a second gating device having a control electrode and two controlled electrodes, a first one of the controlled electrodes being connected to the first clock conductor, and the control electrode being connected to the first controlled electrode of the first gating device; and a single capacitor connected between the second clock conductor and the first controlled electrode of the first gating device.

Claim 25

In combination: two clock conductors; a first gating device having a control electrode and two controlled electrodes, the control electrode being connected to a first clock conductor; a first storage device connected to a first controlled electrode of the first gating device; a second gating device having a control electrode and two controlled electrodes, a first one of the controlled electrodes being connected to the first clock conductor, and the control electrode being connected to the first controlled electrode of the first gating device; and a single capacitor connected between the second clock conductor and the first controlled electrode of the first gating device.