US3586875A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic shift and storage register
Assignee: Electronic Arrays Inc
•
Filing: 1968-09-19
•
Granted: 1971-06-22
•
Expires: 1988-09-19
Abstract
Abstract A dynamic shift register, for example, of the large scale integrated circuit, MOS transistor-type, is described which can be operated as quasi-static register in that each bit circulates within the same stage by operation of separate clock operating for interstage shifting in the dynamic mode but inhibited during the static mode.
Inventors
- 👤 James P Nicklas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 02:23
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
474 words
A storage register operated through a power supply with source of reference potential and having a plurality of stages on an integrated circuit chip, the stages serially interconnected input-to-output as to adjacent stages, each stage including a pair of first and second substages, each substage having normally isolated input and output terminals, the first substage of a pair receiving at its input terminal as input signal the output of the respective preceding stage, and having its output terminal connected to the input terminal of the second substage of the pair, the second substage of the pair providing an output signal as input to the respective succeeding stage of the register, the improvement comprising: means in each substage defining a node that is normally isolated from the remainder of the substage; a clock terminal for each substage, for respectively and alternatingly receiving clock pulses for charging the nodes, the nodes of the two substages of a stage charged by alternating clock pulses; means in each substage responding to the respective clock pulses interspaced with those charging the respective node of the substage for respectively transferring the input signal as received by the respective substage to the respective next substage at the time of a clock pulse the node of the next substage is charged, the substages being constructed in that their respective output terminals are capacitively isolated from each other and isolated from the path-supplying reference potential when clock pulses are not received by the substage, to hold the respective transferred signal; first means connected for coupling the respective second substage of a stage of the plurality to the input terminal of the respective first substage to transfer a signal representing the input of the second substage and constituting the output thereof to the input of the first substage upon reception of particular hold clock pulses concurring with the clock pulses that charge the node of the first substage; transistor means in each substage operated by the clock pulses in phase opposition to those charging the respective node and connected to the node for selective discharge in dependence upon the input signal effective at the input of the respective substage; second means for coupling the output of the second substage of a stage of the plurality to the input of the first substage of the next stage; means outside of the substages for selectively blocking the reception of the hold clock pulses; and means for applying shift clock pulses to the second means for coupling, the shift clock pulses concurring with those controlling the selective discharge of the node of the second substage as being interspaced with the clock pulses as provided to the clock terminal of the first substage, to effect the transfer of the signal representing the input of the second stage to the input of the first substage of the next stage.
Claim 2
Dependent Claim
474 words
A storage register operated through a power supply with source of reference potential and having a plurality of stages on an integrated circuit chip, the stages serially interconnected input-to-output as to adjacent stages, each stage including a pair of first and second substages, each substage having normally isolated input and output terminals, the first substage of a pair receiving at its input terminal as input signal the output of the respective preceding stage, and having its output terminal connected to the input terminal of the second substage of the pair, the second substage of the pair providing an output signal as input to the respective succeeding stage of the register, the improvement comprising: means in each substage defining a node that is normally isolated from the remainder of the substage; a clock terminal for each substage, for respectively and alternatingly receiving clock pulses for charging the nodes, the nodes of the two substages of a stage charged by alternating clock pulses; means in each substage responding to the respective clock pulses interspaced with those charging the respective node of the substage for respectively transferring the input signal as received by the respective substage to the respective next substage at the time of a clock pulse the node of the next substage is charged, the substages being constructed in that their respective output terminals are capacitively isolated from each other and isolated from the path-supplying reference potential when clock pulses are not received by the substage, to hold the respective transferred signal; first means connected for coupling the respective second substage of a stage of the plurality to the input terminal of the respective first substage to transfer a signal representing the input of the second substage and constituting the output thereof to the input of the first substage upon reception of particular hold clock pulses concurring with the clock pulses that charge the node of the first substage; transistor means in each substage operated by the clock pulses in phase opposition to those charging the respective node and connected to the node for selective discharge in dependence upon the input signal effective at the input of the respective substage; second means for coupling the output of the second substage of a stage of the plurality to the input of the first substage of the next stage; means outside of the substages for selectively blocking the reception of the hold clock pulses; and means for applying shift clock pulses to the second means for coupling, the shift clock pulses concurring with those controlling the selective discharge of the node of the second substage as being interspaced with the clock pulses as provided to the clock terminal of the first substage, to effect the transfer of the signal representing the input of the second stage to the input of the first substage of the next stage.
Claim 3
Dependent Claim
468 words
In integrated circuit register comprising: pluralities of first, second, third and fourth regions, isolated from each other by adjoining regions and each having capacitance relative to the respectively adjoining regions, not pertaining to the pluralities; first switching means respectively interconnecting in pairs one of the first and one of the second regions each and concurrently in response to pulses of a first train; second switching means respectively connecting in pairs and concurrently one of the third and one of the fourth regions in response to pulses of a second train; third switching means respectively connecting in different pairs from the connections of the second switching means one of the third and one of the fourth regions in response to pulses of a third train; fourth switching means for permitting coupling of the first regions to potential of a substrate in the integrated circuit only respectively during pulses of the second or third train; fifth switching means included in the second switching means for permitting coupling of the second regions to potential of the substrate in the integrated circuit only respectively during pulses of the first train; first means connected for periodically, alternatingly restoring capacitive charges of the plurality of first and third regions in synchronism respectively with pulses of the second or third and of the first train; second means including the fifths switching means and connected to be responsive to the pulses of the second or third train for controlling the capacitive charges of each of the third regions respectively in dependence upon the level of charges of the second regions in particular association of each of the third regions of the plurality with a second region of the plurality; third means including the fourth switching means connected to be responsive to the pulses of the first train for controlling the maintaining or removal of capacitive charges of each of the first regions in dependence upon the respective ones of the fourth regions being at times respectively connected to one of the third regions by operation of a second train pulse, the respective latter third region being associated with a second region by operation of the second means, and the second switching means which second region is associated with the first region by operation of the first switching means; means also including the fourth switching means and connected to be responsive to the pulses of the third train for controlling the capacitance charges of each of the first regions in dependence upon the respective ones of the fourth regions being at times respectively connected to one of the third regions by operation of a third train pulse; and means for controlling production of the first, second and third trains for providing alternating interspaced sequences of the first and second trains or of the first and third trains.
Claim 4
Dependent Claim
468 words
In integrated circuit register comprising: pluralities of first, second, third and fourth regions, isolated from each other by adjoining regions and each having capacitance relative to the respectively adjoining regions, not pertaining to the pluralities; first switching means respectively interconnecting in pairs one of the first and one of the second regions each and concurrently in response to pulses of a first train; second switching means respectively connecting in pairs and concurrently one of the third and one of the fourth regions in response to pulses of a second train; third switching means respectively connecting in different pairs from the connections of the second switching means one of the third and one of the fourth regions in response to pulses of a third train; fourth switching means for permitting coupling of the first regions to potential of a substrate in the integrated circuit only respectively during pulses of the second or third train; fifth switching means included in the second switching means for permitting coupling of the second regions to potential of the substrate in the integrated circuit only respectively during pulses of the first train; first means connected for periodically, alternatingly restoring capacitive charges of the plurality of first and third regions in synchronism respectively with pulses of the second or third and of the first train; second means including the fifths switching means and connected to be responsive to the pulses of the second or third train for controlling the capacitive charges of each of the third regions respectively in dependence upon the level of charges of the second regions in particular association of each of the third regions of the plurality with a second region of the plurality; third means including the fourth switching means connected to be responsive to the pulses of the first train for controlling the maintaining or removal of capacitive charges of each of the first regions in dependence upon the respective ones of the fourth regions being at times respectively connected to one of the third regions by operation of a second train pulse, the respective latter third region being associated with a second region by operation of the second means, and the second switching means which second region is associated with the first region by operation of the first switching means; means also including the fourth switching means and connected to be responsive to the pulses of the third train for controlling the capacitance charges of each of the first regions in dependence upon the respective ones of the fourth regions being at times respectively connected to one of the third regions by operation of a third train pulse; and means for controlling production of the first, second and third trains for providing alternating interspaced sequences of the first and second trains or of the first and third trains.
Claim 5
Dependent Claim
445 words
A register with integrated circuit bit storage locations comprising; first means defining a source of data bits; second means providing an alternating sequence of first and second phase signals; third means for providing shift phase signals concurring with the first phase signals; fourth means for providing hold phase signals concurring with the first phase signals; fifths means connected for enabling one of the third or the fourth means so that only shift or hold phase signals are provided, Thereby establishing the shift or quasi-static mode respectively; a plurality of bit storage stages, each having input and output terminals, the stages connected serially to each other, the output of one to the input of the next one, the first one having its input connected to the first means; each bit storage stage having first and second substages and respective first substage having first transistor means and second, third and fourth field effect transistors of similar type, each having two main electrodes and a gate, the first transistor means connected with one main electrode to a first node to charge the node in response to the first phase signals applied to the gate, the second transistor connected with one main electrode to ground, the third transistor connected with its main electrodes between the node and the other main electrode of the second transistor, the gate of the second transistor defining the input of the stage; the second substage having fifths transistor means, sixth, seventh and eighth transistors, each having two main electrodes and gate, and ninth transistor means, all of similar type, the fifth transistor means connected to a second node to charge the node in response to each second phase signal, the sixth transistor having one main electrode connected to ground, the fourth transistor of the first substage connecting with its main electrodes the first node to the gate of the sixth transistor, the gate of the fourth transistor connected to the second means to receive therefrom the second phase signals only, the seventh transistor connected with its two main electrodes between the second node and the gate of the second transistor, and having its gate connected to the fourth means to receive therefrom hold phase signals when provided, to couple the second node to the gate of the second transistor in synchronism therewith, the eighth transistor having one main electrode connected to the third means to receive therefrom shift phase signals when provided, the other main electrode defining the output terminal of the stage, the ninth transistor means connecting the second node to the other main electrode of the sixth transistor and having gate means connected for control in synchronism with the first phase pulses.
Claim 6
Dependent Claim
445 words
A register with integrated circuit bit storage locations comprising; first means defining a source of data bits; second means providing an alternating sequence of first and second phase signals; third means for providing shift phase signals concurring with the first phase signals; fourth means for providing hold phase signals concurring with the first phase signals; fifths means connected for enabling one of the third or the fourth means so that only shift or hold phase signals are provided, Thereby establishing the shift or quasi-static mode respectively; a plurality of bit storage stages, each having input and output terminals, the stages connected serially to each other, the output of one to the input of the next one, the first one having its input connected to the first means; each bit storage stage having first and second substages and respective first substage having first transistor means and second, third and fourth field effect transistors of similar type, each having two main electrodes and a gate, the first transistor means connected with one main electrode to a first node to charge the node in response to the first phase signals applied to the gate, the second transistor connected with one main electrode to ground, the third transistor connected with its main electrodes between the node and the other main electrode of the second transistor, the gate of the second transistor defining the input of the stage; the second substage having fifths transistor means, sixth, seventh and eighth transistors, each having two main electrodes and gate, and ninth transistor means, all of similar type, the fifth transistor means connected to a second node to charge the node in response to each second phase signal, the sixth transistor having one main electrode connected to ground, the fourth transistor of the first substage connecting with its main electrodes the first node to the gate of the sixth transistor, the gate of the fourth transistor connected to the second means to receive therefrom the second phase signals only, the seventh transistor connected with its two main electrodes between the second node and the gate of the second transistor, and having its gate connected to the fourth means to receive therefrom hold phase signals when provided, to couple the second node to the gate of the second transistor in synchronism therewith, the eighth transistor having one main electrode connected to the third means to receive therefrom shift phase signals when provided, the other main electrode defining the output terminal of the stage, the ninth transistor means connecting the second node to the other main electrode of the sixth transistor and having gate means connected for control in synchronism with the first phase pulses.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-21 | 1974-12-21 | 1975-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-21 | 1978-12-21 | 1979-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-21 | 1982-12-21 | 1983-06-22 | $7700.00 | Window Closed / Lapsed |