US20030157764A1
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US
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Evaporated LaA1O3 films for gate dielectrics
Assignee: Micron Technology Inc
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Filing: 2002-02-20
•
Granted: —
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Expires: 2022-02-20
Abstract
Abstract A gate dielectric containing LaAlO 3 and method of fabricating a gate dielectric contained LaAlO 3 produce a reliable gate dielectric having a thinner equivalent oxide thickness than attainable using SiO 2 . The LaAlO 3 gate dielectrics formed are thermodynamically stable such that these gate dielectrics will have minimal reactions with a silicon substrate or other structures during processing. A LaAlO 3 gate dielectric is formed by evaporating Al 2 O 3 at a given rate, evaporating La 2 O 3 at another rate, and controlling the two rates to provide an amorphous film containing LaAlO 3 on a transistor body region. The evaporation deposition of the LaAlO 3 film is performed using two electron guns to evaporate dry pellets of Al 2 O 3 and La 2 O 3 . The two rates for evaporating the materials are selectively chosen to provide a dielectric film composition having a predetermined dielectric constant ranging from the dielectric constant of an Al 2 O 3 film to the dielectric constant of a La 2 O 3 film. In addition to forming a LaAlO 3 gate dielectric for a transistor, memory devices, and information handling devices such as computers include elements having a LaAlO 3 gate electric with a thin equivalent oxide thickness.
Inventors
- 👤 Kie Ahn
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:25
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D64/01342; H10D64/60; H10D64/66; H10D64/68; H10D64/691; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6332; H10P14/69; H10P14/692; H10P14/6938; H10P14/6939; H10P14/69391; H10P14/69396; H10P14/69397
Claims Analysis
Total Claims: 77
Claim 1
Independent Claim
54 words
1 . A method of forming a gate dielectric on a transistor body region, comprising: evaporating Al 2 O 3 at a first rate; evaporating La 2 O 3 at a second rate; and controlling the first rate and the second rate to provide a film containing LaAlO 3 on the transistor body region.
Claim 2
Dependent Claim
54 words
1 . A method of forming a gate dielectric on a transistor body region, comprising: evaporating Al 2 O 3 at a first rate; evaporating La 2 O 3 at a second rate; and controlling the first rate and the second rate to provide a film containing LaAlO 3 on the transistor body region.
Claim 3
Dependent Claim
35 words
2 . The method of claim 1 , wherein evaporating Al 2 O 3 and evaporating La 2 O 3 includes evaporating dry pellets of Al 2 O 3 and La 2 O 3 .
Claim 4
Dependent Claim
24 words
3 . The method of claim 1 , wherein evaporating La 2 O 3 includes evaporating La 2 O 3 by electron beam evaporation.
Claim 5
Dependent Claim
37 words
4 . The method of claim 1 , wherein controlling the first rate and the second rate includes controlling the first rate and the second rate to selectively provide a film composition having a predetermined dielectric constant.
Claim 6
Dependent Claim
51 words
5 . The method of claim 4 , wherein selectively providing a film composition having a predetermined dielectric constant includes providing a film composition with a dielectric constant ranging from the dielectric constant of an Al 2 O 3 film to the dielectric constant of a La 2 O 3 film.
Claim 7
Dependent Claim
31 words
6 . The method of claim 1 , wherein controlling the first rate and the second rate to provide a film containing LaAlO 3 includes providing an amorphous LaAlO 3 film.
Claim 8
Dependent Claim
25 words
7 . The method of claim 1 , wherein evaporating La 2 O 3 begins substantially concurrent with beginning evaporating Al 2 O 3 .
Claim 9
Dependent Claim
50 words
8 . The method of claim 1 , wherein evaporating Al 2 O 3 and evaporating La 2 O 3 includes depositing LaAlO 3 on the transistor body region in a base pressure lower than about 5×10 −7 Torr and in a deposition pressure lower than about 2×10 −6 Torr.
Claim 10
Dependent Claim
23 words
9 . The method of claim 1 , further including annealing the transistor body region after providing the film containing LaAlO 3 .
Claim 11
Dependent Claim
27 words
10 . The method of claim 9 , wherein annealing the transistor body region after providing the film containing LaAlO 3 includes annealing in N 2 .
Claim 12
Dependent Claim
23 words
11 . The method of claim 10 , wherein annealing in N 2 includes annealing in an electric furnace at about 700° C.
Claim 13
Dependent Claim
28 words
12 . The method of claim 10 , wherein annealing in N 2 includes annealing in RTA in the range from about 800° C. to about 900° C.
Claim 14
Dependent Claim
64 words
13 . A method of forming a gate dielectric on a transistor body region, comprising: evaporating Al 2 O 3 at a first rate using a first electron gun; evaporating La 2 O 3 at a second rate using a second electron gun; and controlling the first rate and the second rate to provide a film containing LaAlO 3 on the transistor body region.
Claim 15
Dependent Claim
64 words
13 . A method of forming a gate dielectric on a transistor body region, comprising: evaporating Al 2 O 3 at a first rate using a first electron gun; evaporating La 2 O 3 at a second rate using a second electron gun; and controlling the first rate and the second rate to provide a film containing LaAlO 3 on the transistor body region.
Claim 16
Dependent Claim
35 words
14 . The method of claim 13 , wherein evaporating Al 2 O 3 and evaporating La 2 O 3 includes evaporating dry pellets of Al 2 O 3 and La 2 O 3 .
Claim 17
Dependent Claim
37 words
15 . The method of claim 13 , wherein controlling the first rate and the second rate includes controlling the first rate and the second rate to selectively provide a film composition having a predetermined dielectric constant.
Claim 18
Dependent Claim
51 words
16 . The method of claim 15 , wherein selectively providing a film composition having a predetermined dielectric constant includes providing a film composition with a dielectric constant ranging from the dielectric constant of an Al 2 O 3 film to the dielectric constant of a La 2 O 3 film.
Claim 19
Dependent Claim
31 words
17 . The method of claim 13 , wherein controlling the first rate and the second rate to provide a film containing LaAlO 3 includes providing an amorphous LaAlO 3 film.
Claim 20
Dependent Claim
25 words
18 . The method of claim 13 , wherein evaporating La 2 O 3 begins substantially concurrent with beginning evaporating Al 2 O 3 .
Claim 21
Dependent Claim
35 words
19 . The method of claim 13 , wherein forming the gate dielectric includes growing the film containing LaAlO 3 at a growth rate in the range from about 0.5 nm/min to about 50 nm/min.
Claim 22
Dependent Claim
23 words
20 . The method of claim 13 , further including annealing the transistor body region after providing the film containing LaAlO 3 .
Claim 23
Dependent Claim
80 words
21 . A method of forming a gate dielectric on a transistor body region, comprising: evaporating Al 2 O 3 at a first rate using a first electron gun; evaporating La 2 O 3 at a second rate using a second electron gun; controlling the first rate and the second rate to provide a film containing LaAlO 3 on the transistor body region; and annealing in N 2 after providing the film containing LaAlO 3 on the transistor body region.
Claim 24
Dependent Claim
80 words
21 . A method of forming a gate dielectric on a transistor body region, comprising: evaporating Al 2 O 3 at a first rate using a first electron gun; evaporating La 2 O 3 at a second rate using a second electron gun; controlling the first rate and the second rate to provide a film containing LaAlO 3 on the transistor body region; and annealing in N 2 after providing the film containing LaAlO 3 on the transistor body region.
Claim 25
Dependent Claim
35 words
22 . The method of claim 21 , wherein evaporating Al 2 O 3 and evaporating La 2 O 3 includes evaporating dry pellets of Al 2 O 3 and La 2 O 3 .
Claim 26
Dependent Claim
37 words
23 . The method of claim 21 , wherein controlling the first rate and the second rate includes controlling the first rate and the second rate to selectively provide a film composition having a predetermined dielectric constant.
Claim 27
Dependent Claim
31 words
24 . The method of claim 21 , wherein controlling the first rate and the second rate to provide a film containing LaAlO 3 includes providing an amorphous LaAlO 3 film.
Claim 28
Dependent Claim
25 words
25 . The method of claim 21 , wherein evaporating La 2 O 3 begins substantially concurrent with beginning evaporating Al 2 O 3 .
Claim 29
Dependent Claim
50 words
26 . The method of claim 21 , wherein evaporating Al 2 O 3 and evaporating La 2 O 3 includes depositing LaAlO 3 on the transistor body region in a base pressure lower than about 5×10 −7 Torr and in a deposition pressure lower than about 2×10 −6 Torr.
Claim 30
Dependent Claim
23 words
27 . The method of claim 21 , wherein annealing in N 2 includes annealing in an electric furnace at about 700° C.
Claim 31
Dependent Claim
35 words
28 . The method of claim 21 , wherein forming the gate dielectric includes growing the film containing LaAlO 3 at a growth rate in the range from about 0.5 nm/min to about 50 nm/min.
Claim 32
Dependent Claim
74 words
29 . A method of forming a transistor, comprising: forming first and second source/drain regions; forming a body region between the first and second source/drain regions; evaporating Al 2 O 3 at a first rate; evaporating La 2 O 3 at a second rate; controlling the first rate and the second rate to provide a film containing LaAlO 3 on the body region; and coupling a gate to the film containing LaAlO 3 .
Claim 33
Dependent Claim
74 words
29 . A method of forming a transistor, comprising: forming first and second source/drain regions; forming a body region between the first and second source/drain regions; evaporating Al 2 O 3 at a first rate; evaporating La 2 O 3 at a second rate; controlling the first rate and the second rate to provide a film containing LaAlO 3 on the body region; and coupling a gate to the film containing LaAlO 3 .
Claim 34
Dependent Claim
35 words
30 . The method of claim 29 , wherein evaporating Al 2 O 3 and evaporating La 2 O 3 includes evaporating dry pellets of Al 2 O 3 and La 2 O 3 .
Claim 35
Dependent Claim
37 words
31 . The method of claim 29 , wherein controlling the first rate and the second rate includes controlling the first rate and the second rate to selectively provide a film composition having a predetermined dielectric constant.
Claim 36
Dependent Claim
51 words
32 . The method of claim 29 , wherein selectively providing a film composition having a predetermined dielectric constant includes providing a film composition with a dielectric constant ranging from the dielectric constant of an Al 2 O 3 film to the dielectric constant of a La 2 O 3 film.
Claim 37
Dependent Claim
31 words
33 . The method of claim 29 , wherein controlling the first rate and the second rate to provide a film containing LaAlO 3 includes providing an amorphous LaAlO 3 film.
Claim 38
Dependent Claim
25 words
34 . The method of claim 29 , wherein evaporating La 2 O 3 begins substantially concurrent with beginning evaporating Al 2 O 3 .
Claim 39
Dependent Claim
141 words
35 . A method of forming a memory array, comprising: forming a number of access transistors, comprising: forming first and second source/drain regions; forming a body region between the first and second source/drain regions; evaporating Al 2 O 3 at a first rate; evaporating La 2 O 3 at a second rate; controlling the first rate and the second rate to provide a film containing LaAlO 3 on the body region.; and coupling a gate to the film containing LaAlO 3 ; forming a number of wordlines coupled to a number of the gates of the number of access transistors; forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
Claim 40
Dependent Claim
141 words
35 . A method of forming a memory array, comprising: forming a number of access transistors, comprising: forming first and second source/drain regions; forming a body region between the first and second source/drain regions; evaporating Al 2 O 3 at a first rate; evaporating La 2 O 3 at a second rate; controlling the first rate and the second rate to provide a film containing LaAlO 3 on the body region.; and coupling a gate to the film containing LaAlO 3 ; forming a number of wordlines coupled to a number of the gates of the number of access transistors; forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
Claim 41
Dependent Claim
35 words
36 . The method of claim 35 , wherein evaporating Al 2 O 3 and evaporating La 2 O 3 includes evaporating dry pellets of Al 2 O 3 and La 2 O 3 .
Claim 42
Dependent Claim
37 words
37 . The method of claim 35 , wherein controlling the first rate and the second rate includes controlling the first rate and the second rate to selectively provide a film composition having a predetermined dielectric constant.
Claim 43
Dependent Claim
51 words
38 . The method of claim 37 , wherein selectively providing a film composition having a predetermined dielectric constant includes providing a film composition with a dielectric constant ranging from the dielectric constant of an Al 2 O 3 film to the dielectric constant of a La 2 O 3 film.
Claim 44
Dependent Claim
35 words
39 . The method of claim 35 , wherein forming the gate dielectric includes growing the film containing LaAlO 3 at a growth rate in the range from about 0.5 nm/min to about 50 nm/min.
Claim 45
Dependent Claim
162 words
40 . A method of forming an information handling system, comprising: forming a processor; forming a memory array, comprising: forming a number of access transistors, comprising: forming first and second source/drain regions; forming a body region between the first and second source/drain regions; evaporating Al 2 O 3 at a first rate; evaporating La 2 O 3 at a second rate; controlling the first rate and the second rate to provide a film containing LaAlO 3 on the body region.; and coupling a gate to the film containing LaAlO 3 ; forming a number of wordlines coupled to a number of the gates of the number of access transistors; forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors; and forming a system bus that couples the processor to the memory array.
Claim 46
Dependent Claim
162 words
40 . A method of forming an information handling system, comprising: forming a processor; forming a memory array, comprising: forming a number of access transistors, comprising: forming first and second source/drain regions; forming a body region between the first and second source/drain regions; evaporating Al 2 O 3 at a first rate; evaporating La 2 O 3 at a second rate; controlling the first rate and the second rate to provide a film containing LaAlO 3 on the body region.; and coupling a gate to the film containing LaAlO 3 ; forming a number of wordlines coupled to a number of the gates of the number of access transistors; forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors; and forming a system bus that couples the processor to the memory array.
Claim 47
Dependent Claim
35 words
41 . The method of claim 40 , wherein evaporating Al 2 O 3 and evaporating La 2 O 3 includes evaporating dry pellets of Al 2 O 3 and La 2 O 3 .
Claim 48
Dependent Claim
36 words
42 . The method of claim 40 , wherein evaporating La 2 O 3 and evaporating Al 2 O 3 includes evaporating La 2 O 3 and evaporating Al 2 O 3 by electron beam evaporation.
Claim 49
Dependent Claim
37 words
43 . The method of claim 40 , wherein controlling the first rate and the second rate includes controlling the first rate and the second rate to selectively provide a film composition having a predetermined dielectric constant.
Claim 50
Dependent Claim
67 words
44 . A transistor, comprising: a first and second source/drain region; a body region located between the first and second source/drain regions; a dielectric layer containing LaAlO 3 coupled to a surface portion of the body region between the first and second source/drain regions, the dielectric layer including Al 2 O 3 , or La 2 O 3 ; and a gate coupled to the dielectric layer.
Claim 51
Dependent Claim
67 words
44 . A transistor, comprising: a first and second source/drain region; a body region located between the first and second source/drain regions; a dielectric layer containing LaAlO 3 coupled to a surface portion of the body region between the first and second source/drain regions, the dielectric layer including Al 2 O 3 , or La 2 O 3 ; and a gate coupled to the dielectric layer.
Claim 52
Dependent Claim
24 words
45 . The transistor of claim 44 , wherein the dielectric layer includes Al 2 O 3 , and La 2 O 3 .
Claim 53
Dependent Claim
15 words
46 . The transistor of claim 44 , wherein the dielectric layer is substantially amorphous.
Claim 54
Dependent Claim
25 words
47 . The transistor of claim 44 , wherein the dielectric layer exhibits a dielectric constant in the range from about 21 to about 25.
Claim 55
Dependent Claim
31 words
48 . The transistor of claim 44 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) in the range from about 1.5 Angstroms to about 5 Angstroms.
Claim 56
Dependent Claim
25 words
49 . The transistor of claim 44 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) of less than 3 Angstroms.
Claim 57
Dependent Claim
130 words
50 . A memory array, comprising: a number of access transistors, comprising: a first and second source/drain region; a body region located between the first and second source/drain regions; a dielectric layer containing LaAlO 3 coupled to a surface portion of the body region between the first and second source/drain regions, the dielectric layer including Al 2 O 3 , or La 2 O 3 ; and a gate coupled to the dielectric layer; a number of wordlines coupled to a number of the gates of the number of access transistors; a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
Claim 58
Dependent Claim
130 words
50 . A memory array, comprising: a number of access transistors, comprising: a first and second source/drain region; a body region located between the first and second source/drain regions; a dielectric layer containing LaAlO 3 coupled to a surface portion of the body region between the first and second source/drain regions, the dielectric layer including Al 2 O 3 , or La 2 O 3 ; and a gate coupled to the dielectric layer; a number of wordlines coupled to a number of the gates of the number of access transistors; a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
Claim 59
Dependent Claim
25 words
51 . The memory array of claim 50 , wherein the dielectric layer includes Al 2 O 3 , and La 2 O 3 .
Claim 60
Dependent Claim
16 words
52 . The memory array of claim 50 , wherein the dielectric layer is substantially amorphous.
Claim 61
Dependent Claim
26 words
53 . The memory array of claim 50 , wherein the dielectric layer exhibits a dielectric constant in the range from about 21 to about 25.
Claim 62
Dependent Claim
32 words
54 . The memory array of claim 50 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) in the range from about 1.5 Angstroms to about 5 Angstroms.
Claim 63
Dependent Claim
26 words
55 . The memory array of claim 50 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) of less than 3 Angstroms.
Claim 64
Dependent Claim
147 words
56 . An information handling device, comprising: a processor; a memory array, comprising: a number of access transistors, comprising: a first and second source/drain region; a body region located between the first and second source/drain regions; a dielectric layer containing LaAlO 3 coupled to a surface portion of the body region between the first and second source/drain regions, the dielectric layer including Al 2 O 3 , or La 2 O 3 ; and a gate coupled to the dielectric layer; a number of wordlines coupled to a number of the gates of the number of access transistors; a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors; and a system bus coupling the processor to the memory device.
Claim 65
Dependent Claim
147 words
56 . An information handling device, comprising: a processor; a memory array, comprising: a number of access transistors, comprising: a first and second source/drain region; a body region located between the first and second source/drain regions; a dielectric layer containing LaAlO 3 coupled to a surface portion of the body region between the first and second source/drain regions, the dielectric layer including Al 2 O 3 , or La 2 O 3 ; and a gate coupled to the dielectric layer; a number of wordlines coupled to a number of the gates of the number of access transistors; a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors; and a system bus coupling the processor to the memory device.
Claim 66
Dependent Claim
26 words
57 . The information handling device of claim 56 , wherein the dielectric layer includes Al 2 O 3 , and La 2 O 3 .
Claim 67
Dependent Claim
17 words
58 . The information handling device of claim 56 , wherein the dielectric layer is substantially amorphous.
Claim 68
Dependent Claim
27 words
59 . The information handling device of claim 56 , wherein the dielectric layer exhibits a dielectric constant in the range from about 21 to about 25.
Claim 69
Dependent Claim
33 words
60 . The information handling device of claim 56 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) in the range from about 1.5 Angstroms to about 5 Angstroms.
Claim 70
Dependent Claim
27 words
61 . The information handling device of claim 56 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) of less than 3 Angstroms.
Claim 71
Dependent Claim
72 words
62 . A transistor formed by the process, comprising: forming a body region coupled between a first source/drain region and a second source/drain region; evaporating Al 2 O 3 at a first rate; evaporating La 2 O 3 at a second rate; controlling the first rate and the second rate to provide a film containing LaAlO 3 on the body region; and coupling a gate to the film containing LaAlO 3 .
Claim 72
Dependent Claim
72 words
62 . A transistor formed by the process, comprising: forming a body region coupled between a first source/drain region and a second source/drain region; evaporating Al 2 O 3 at a first rate; evaporating La 2 O 3 at a second rate; controlling the first rate and the second rate to provide a film containing LaAlO 3 on the body region; and coupling a gate to the film containing LaAlO 3 .
Claim 73
Dependent Claim
35 words
63 . The transistor of claim 62 , wherein evaporating Al 2 O 3 and evaporating La 2 O 3 includes evaporating dry pellets of Al 2 O 3 and La 2 O 3 .
Claim 74
Dependent Claim
42 words
64 . The transistor of claim 62 , wherein evaporating Al 2 O 3 and evaporating La 2 O 3 includes evaporating Al 2 O 3 using a first electron gun and evaporating La 2 O 3 using a second electron gun.
Claim 75
Dependent Claim
37 words
65 . The transistor of claim 62 , wherein controlling the first rate and the second rate includes controlling the first rate and the second rate to selectively provide a film composition having a predetermined dielectric constant.
Claim 76
Dependent Claim
25 words
66 . The transistor of claim 62 , wherein the dielectric layer exhibits a dielectric constant in the range from about 21 to about 25.
Claim 77
Dependent Claim
31 words
67 . The transistor of claim 62 , wherein the dielectric layer exhibits an equivalent oxide thickness (t eq ) in the range from about 1.5 Angstroms to about 5 Angstroms.
References Cited (Backward Citations)
US4394673A
Cited
US6057271A
Cited
US6110529A
Cited
US5840897A
Cited
US5302461A
Cited
US5810923A
Cited
US5828080A
Cited
US5625233A
Cited
US5801105A
Cited
US6387712B1
Cited
US5698022A
Cited
US6203726B1
Cited
US6699745B1
Cited
US6093944A
Cited
US6207589B1
Cited
US6297539B1
Cited
US6040243A
Cited
US6203613B1
Cited
US6531354B2
Cited
US6527866B1
Cited
US6627503B2
Cited
US6432779B1
Cited
US6521911B2
Cited
US6300203B1
Cited
US6465334B1
Cited
US6495436B2
Cited
US20020146916A1
Cited
US20020155688A1
Cited
US6514828B2
Cited
US20020155689A1
Cited
US20020192974A1
Cited
US6534420B2
Cited
US20030017717A1
Cited
US6461914B1
Cited
US6451662B1
Cited
US6683011B2
Cited
US20030119291A1
Cited
US6696332B2
Cited
US6645882B1
Cited
US6620670B2
Cited
US20030207593A1
Cited
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