US20030119291A1
Expired / Lapsed
US
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Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics
Assignee: Micron Technology Inc
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Filing: 2001-12-20
•
Granted: —
•
Expires: 2021-12-20
Abstract
Abstract A praseodymium (Pr) gate oxide and method of fabricating same that produces a high-quality and ultra-thin equivalent oxide thickness as compared to conventional SiO 2 gate oxides are provided. The Pr gate oxide is thermodynamically stable so that the oxide reacts minimally with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit a Pr layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
Inventors
- 👤 Kie Ahn
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:02
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6314; C; C23; C23C; C23C14/00; C23C14/06; C23C14/14; C23C14/16; C23C14/58; C23C14/5826; C23C14/5846; C23C14/5853; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D64/01342; H10D64/60; H10D64/66; H10D64/68; H10D64/691; H10P14/40; H10P14/6319; H10P14/6322; H10P14/69; H10P14/692; H10P14/6938; H10P14/6939; H10P14/69396
Claims Analysis
Total Claims: 64
Claim 1
Independent Claim
42 words
1 . A method of forming a gate oxide on a transistor body region, comprising: evaporation depositing a praseodymium (Pr) layer on the body region; and oxidizing the Pr layer to form a Pr 2 O 3 layer on the body region.
Claim 2
Dependent Claim
42 words
1 . A method of forming a gate oxide on a transistor body region, comprising: evaporation depositing a praseodymium (Pr) layer on the body region; and oxidizing the Pr layer to form a Pr 2 O 3 layer on the body region.
Claim 3
Dependent Claim
21 words
2 . The method of claim 1 , wherein evaporation depositing the Pr layer includes evaporation depositing by electron beam evaporation.
Claim 4
Dependent Claim
25 words
3 . The method of claim 2 , wherein electron beam evaporation depositing the Pr layer includes electron beam evaporating a 99.9999% pure Pr target.
Claim 5
Dependent Claim
26 words
4 . The method of claim 1 , wherein evaporation depositing the Pr layer includes evaporation depositing at an approximate substrate temperature range of 150-400° C.
Claim 6
Dependent Claim
22 words
5 . The method of claim 1 , wherein oxidizing the Pr layer includes oxidizing at a temperature of approximately 400° C.
Claim 7
Dependent Claim
18 words
6 . The method of claim 1 , wherein oxidizing the Pr layer includes oxidizing with atomic oxygen.
Claim 8
Dependent Claim
25 words
7 . The method of claim 1 , wherein oxidizing the Pr layer includes oxidizing using a krypton (Kr)/oxygen (O 2 ) mixed plasma process.
Claim 9
Dependent Claim
31 words
8 . The method of claim 1 , wherein the method includes forming the Pr 2 O 3 layer to have an equivalent oxide thickness (EOT) of less than 2 nm.
Claim 10
Dependent Claim
53 words
9 . A method of forming a gate oxide on a transistor body region, comprising: evaporation depositing a praseodymium (Pr) layer on the body region; and oxidizing the Pr layer using a krypton(Kr)/oxygen (O 2 ) mixed plasma process to form an oxide layer of Pr 2 O 3 on the body region.
Claim 11
Dependent Claim
53 words
9 . A method of forming a gate oxide on a transistor body region, comprising: evaporation depositing a praseodymium (Pr) layer on the body region; and oxidizing the Pr layer using a krypton(Kr)/oxygen (O 2 ) mixed plasma process to form an oxide layer of Pr 2 O 3 on the body region.
Claim 12
Dependent Claim
21 words
10 . The method of claim 9 , wherein evaporation depositing the metal layer includes evaporation depositing by electron beam evaporation.
Claim 13
Dependent Claim
25 words
11 . The method of claim 10 , wherein electron beam evaporation depositing the Pr layer includes electron beam evaporating a 99.9999% pure Pr target.
Claim 14
Dependent Claim
26 words
12 . The method of claim 9 , wherein evaporation depositing the Pr layer includes evaporation depositing at an approximate substrate temperature range of 150-400° C.
Claim 15
Dependent Claim
65 words
13 . A method of forming a transistor, comprising: forming first and second source/drain regions; forming a body region between the first and second source/drain regions; evaporation depositing a praseodymium (Pr) layer on the body region; oxidizing the Pr layer to form a Pr 2 O 3 oxide layer on the body region; and coupling a gate to the Pr 2 O 3 oxide layer.
Claim 16
Dependent Claim
65 words
13 . A method of forming a transistor, comprising: forming first and second source/drain regions; forming a body region between the first and second source/drain regions; evaporation depositing a praseodymium (Pr) layer on the body region; oxidizing the Pr layer to form a Pr 2 O 3 oxide layer on the body region; and coupling a gate to the Pr 2 O 3 oxide layer.
Claim 17
Dependent Claim
21 words
14 . The method of claim 13 , wherein evaporation depositing the Pr layer includes evaporation depositing by electron beam evaporation.
Claim 18
Dependent Claim
25 words
15 . The method of claim 14 , wherein electron beam evaporation depositing the Pr layer includes electron beam evaporating a 99.9999% pure Pr target.
Claim 19
Dependent Claim
26 words
16 . The method of claim 13 , wherein evaporation depositing the Pr layer includes evaporation depositing at an approximate substrate temperature range of 150-400° C.
Claim 20
Dependent Claim
22 words
17 . The method of claim 13 , wherein oxidizing the Pr layer includes oxidizing at a temperature of approximately 400° C.
Claim 21
Dependent Claim
18 words
18 . The method of claim 13 , wherein oxidizing the Pr layer includes oxidizing with atomic oxygen.
Claim 22
Dependent Claim
25 words
19 . The method of claim 13 , wherein oxidizing the Pr layer includes oxidizing using a krypton (Kr)/oxygen (O 2 ) mixed plasma process.
Claim 23
Dependent Claim
131 words
20 . A method of forming a memory array, comprising: forming a number of access transistors, comprising: forming first and second source/drain regions; forming a body region between the first and second source/drain regions; evaporation depositing a praseodymium (Pr) layer on the body region; oxidizing the Pr layer to form a Pr 2 O 3 oxide layer on the body region; coupling a gate to the Pr 2 O 3 oxide layer; forming a number of wordlines coupled to a number of the gates of the number of access transistors; forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
Claim 24
Dependent Claim
131 words
20 . A method of forming a memory array, comprising: forming a number of access transistors, comprising: forming first and second source/drain regions; forming a body region between the first and second source/drain regions; evaporation depositing a praseodymium (Pr) layer on the body region; oxidizing the Pr layer to form a Pr 2 O 3 oxide layer on the body region; coupling a gate to the Pr 2 O 3 oxide layer; forming a number of wordlines coupled to a number of the gates of the number of access transistors; forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
Claim 25
Dependent Claim
21 words
21 . The method of claim 20 , wherein evaporation depositing the Pr layer includes evaporation depositing by electron beam evaporation.
Claim 26
Dependent Claim
25 words
22 . The method of claim 21 , wherein electron beam evaporation depositing the Pr layer includes electron beam evaporating a 99.9999% pure Pr target.
Claim 27
Dependent Claim
26 words
23 . The method of claim 20 , wherein evaporation depositing the Pr layer includes evaporation depositing at an approximate substrate temperature range of 150-400° C.
Claim 28
Dependent Claim
22 words
24 . The method of claim 20 , wherein oxidizing the Pr layer includes oxidizing at a temperature of approximately 400° C.
Claim 29
Dependent Claim
18 words
25 . The method of claim 20 , wherein oxidizing the Pr layer includes oxidizing with atomic oxygen.
Claim 30
Dependent Claim
25 words
26 . The method of claim 20 , wherein oxidizing the Pr layer includes oxidizing using a krypton (Kr)/oxygen (O 2 ) mixed plasma process.
Claim 31
Dependent Claim
152 words
27 . A method of forming an information handling system, comprising: forming a processor; forming a memory array, comprising: forming a number of access transistors, comprising: forming first and second source/drain regions; forming a body region between the first and second source/drain regions; evaporation depositing a praseodymium (Pr) layer on the body region; oxidizing the Pr layer to form a Pr 2 O 3 oxide layer on the body region; coupling a gate to the Pr 2 O 3 oxide layer; forming a number of wordlines coupled to a number of the gates of the number of access transistors; forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors; and forming a system bus that couples the processor to the memory array.
Claim 32
Dependent Claim
152 words
27 . A method of forming an information handling system, comprising: forming a processor; forming a memory array, comprising: forming a number of access transistors, comprising: forming first and second source/drain regions; forming a body region between the first and second source/drain regions; evaporation depositing a praseodymium (Pr) layer on the body region; oxidizing the Pr layer to form a Pr 2 O 3 oxide layer on the body region; coupling a gate to the Pr 2 O 3 oxide layer; forming a number of wordlines coupled to a number of the gates of the number of access transistors; forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors; and forming a system bus that couples the processor to the memory array.
Claim 33
Dependent Claim
21 words
28 . The method of claim 27 , wherein evaporation depositing the Pr layer includes evaporation depositing by electron beam evaporation.
Claim 34
Dependent Claim
26 words
29 . The method of claim 28 , wherein electron beam evaporation depositing the Pr layer includes electron beam evaporation of a 99.9999% pure Pr target.
Claim 35
Dependent Claim
26 words
30 . The method of claim 27 , wherein evaporation depositing the Pr layer includes evaporation depositing at an approximate substrate temperature range of 150-400° C.
Claim 36
Dependent Claim
22 words
31 . The method of claim 27 , wherein oxidizing the Pr layer includes oxidizing at a temperature of approximately 400° C.
Claim 37
Dependent Claim
18 words
32 . The method of claim 27 , wherein oxidizing the Pr layer includes oxidizing with atomic oxygen.
Claim 38
Dependent Claim
25 words
33 . The method of claim 27 , wherein oxidizing the Pr layer includes oxidizing using a krypton (Kr)/oxygen (O 2 ) mixed plasma process.
Claim 39
Dependent Claim
63 words
34 . A transistor, comprising: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0 . 6 nm; a praseodymium oxide dielectric layer coupled to the surface portion of the body region; and a gate coupled to praseodymium oxide dielectric layer.
Claim 40
Dependent Claim
63 words
34 . A transistor, comprising: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0 . 6 nm; a praseodymium oxide dielectric layer coupled to the surface portion of the body region; and a gate coupled to praseodymium oxide dielectric layer.
Claim 41
Dependent Claim
25 words
35 . The transistor of claim 34 , wherein the surface portion of the body region is oriented in a ( 100 ) crystalline plane.
Claim 42
Dependent Claim
25 words
36 . The transistor of claim 34 , wherein the surface portion of the body region is oriented in a ( 111 ) crystalline plane.
Claim 43
Dependent Claim
17 words
37 . The transistor of claim 34 , wherein the praseodymium oxide dielectric layer is substantially amorphous.
Claim 44
Dependent Claim
124 words
38 . A memory array, comprising: a number of access transistors, comprising: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a praseodymium oxide dielectric layer coupled to the surface portion of the body region; a gate coupled to the praseodymium oxide dielectric layer; a number of wordlines coupled to a number of the gates of the number of access transistors; a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
Claim 45
Dependent Claim
124 words
38 . A memory array, comprising: a number of access transistors, comprising: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a praseodymium oxide dielectric layer coupled to the surface portion of the body region; a gate coupled to the praseodymium oxide dielectric layer; a number of wordlines coupled to a number of the gates of the number of access transistors; a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; and a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
Claim 46
Dependent Claim
23 words
39 . The memory array of claim 38 , wherein the praseodymium oxide dielectric layer exhibits a dielectric constant (k) of approximately 31.
Claim 47
Dependent Claim
18 words
40 . The memory array of claim 38 , wherein the praseodymium oxide dielectric layer is substantially amorphous.
Claim 48
Dependent Claim
141 words
41 . An information handling device, comprising: a processor; a memory array, comprising: a number of access transistors, comprising: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a praseodymium oxide dielectric layer coupled to the surface portion of the body region; a gate coupled to the praseodymium oxide dielectric layer; a number of wordlines coupled to a number of the gates of the number of access transistors; a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors; and a system bus coupling the processor to the memory device.
Claim 49
Dependent Claim
141 words
41 . An information handling device, comprising: a processor; a memory array, comprising: a number of access transistors, comprising: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a praseodymium oxide dielectric layer coupled to the surface portion of the body region; a gate coupled to the praseodymium oxide dielectric layer; a number of wordlines coupled to a number of the gates of the number of access transistors; a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors; a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors; and a system bus coupling the processor to the memory device.
Claim 50
Dependent Claim
24 words
42 . The information handling device of claim 41 , wherein the praseodymium oxide dielectric layer exhibits a dielectric constant (k) of approximately 31.
Claim 51
Dependent Claim
19 words
43 . The information handling device of claim 41 , wherein the praseodymium oxide dielectric layer is substantially amorphous.
Claim 52
Dependent Claim
65 words
44 . A transistor formed by the process, comprising: forming a body region coupled between a first source/drain region and a second source/drain region; evaporation depositing a praseodymium (Pr) metal layer on the body region; oxidizing the Pr metal layer to form a Pr 2 O 3 oxide layer on the body region; and coupling a gate to the Pr 2 O 3 oxide layer.
Claim 53
Dependent Claim
65 words
44 . A transistor formed by the process, comprising: forming a body region coupled between a first source/drain region and a second source/drain region; evaporation depositing a praseodymium (Pr) metal layer on the body region; oxidizing the Pr metal layer to form a Pr 2 O 3 oxide layer on the body region; and coupling a gate to the Pr 2 O 3 oxide layer.
Claim 54
Dependent Claim
22 words
45 . The transistor of claim 44 , wherein evaporation depositing the Pr metal layer includes evaporation depositing by electron beam evaporation.
Claim 55
Dependent Claim
26 words
46 . The method of claim 45 , wherein oxidizing the Pr metal layer includes oxidizing using a krypton (Kr)/oxygen (O 2 ) mixed plasma process.
Claim 56
Dependent Claim
46 words
47 . A method of forming a gate oxide on a transistor body region, comprising: electron beam evaporation depositing a layer of praseodymium (Pr) on the body region; and oxidizing the Pr layer to form a Pr 2 O 3 oxide layer on the body region.
Claim 57
Dependent Claim
46 words
47 . A method of forming a gate oxide on a transistor body region, comprising: electron beam evaporation depositing a layer of praseodymium (Pr) on the body region; and oxidizing the Pr layer to form a Pr 2 O 3 oxide layer on the body region.
Claim 58
Dependent Claim
33 words
48 . The method of claim 47 , wherein the method includes oxidizing the Pr layer to form the Pr 2 O 3 oxide to have a thickness of 2 nm or less.
Claim 59
Dependent Claim
23 words
49 . The method of claim 47 , wherein the method includes annealing the Pr 2 O 3 oxide layer at 600° C.
Claim 60
Dependent Claim
79 words
50 . A transistor, comprising: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a Pr 2 O 3 oxide dielectric layer coupled to the surface portion of the body region, wherein the oxide dielectric layer has a dielectric constant of about 31; and a gate coupled to Pr 2 O 3 oxide dielectric layer.
Claim 61
Dependent Claim
79 words
50 . A transistor, comprising: a first and second source/drain region; a body region located between the first and second source/drain regions, wherein a surface portion of the body region has a surface roughness of approximately 0.6 nm; a Pr 2 O 3 oxide dielectric layer coupled to the surface portion of the body region, wherein the oxide dielectric layer has a dielectric constant of about 31; and a gate coupled to Pr 2 O 3 oxide dielectric layer.
Claim 62
Dependent Claim
25 words
51 . The transistor of claim 50 , wherein the surface portion of the body region is oriented in a ( 100 ) crystalline plane.
Claim 63
Dependent Claim
25 words
52 . The transistor of claim 50 , wherein the surface portion of the body region is oriented in a ( 111 ) crystalline plane.
Claim 64
Dependent Claim
20 words
53 . The transistor of claim 50 , wherein the Pr 2 O 3 oxide dielectric layer is substantially amorphous.
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