Three-dimensional silicon interposer for low voltage low power systems

Claim 2

A silicon interposer, comprising: a plurality of through-silicon vias within a first plane of the interposer, wherein the through-silicon vias are adapted to serve as power, ground and signal interconnections throughout the first plane such that the through-silicon vias that serve as the power and ground interconnections are greater in at least one of number and size than the through-silicon vias that serve as the signal interconnections so as to support uniform power distribution during low voltage operations; and a plurality of lines within a second plane of the interposer in contact with one or more of the through-silicon vias in the first plane, the second plane being adjacent to the first plane, wherein the lines are adapted to serve as power, ground and signal interconnections throughout the second plane such that the lines that serve as the power and ground interconnections are greater in at least one of number and size than the lines that serve as the signal interconnections so as to support uniform power distribution during low voltage operations.

Claim 3

The silicon interposer of claim 1 , wherein the through-silicon vias and lines that serve as the power and ground interconnections are present in number and size to support uniform power distribution during low voltage operations of less than 500 millivolts.

Claim 4

The silicon interposer of claim 1 , wherein the through-silicon vias and lines that serve as the power and ground interconnections are present in number and size to support uniform power distribution during low voltage operations of less than 300 millivolts.

Claim 5

The silicon interposer of claim 1 , wherein multiple through-silicon vias serve as each power, ground and signal interconnection throughout the first plane.

Claim 6

The silicon interposer of claim 4 , wherein the multiple through-silicon vias that serve as each signal interconnection throughout the first plane have a pitch that is less than a pitch of the multiple through-silicon vias that serve as each power and ground interconnection throughout the first plane.

Claim 7

The silicon interposer of claim 1 , further comprising at least one voltage regulator module and at least one voltage control module within the second plane of the interposer in contact with one or more of the lines that serve as power and ground interconnections throughout the second plane, wherein the at least one voltage regulator module and the at least one voltage control module are adapted to regulate voltage level through the one or more lines that serve as power and ground interconnections so as to support uniform power distribution during low voltage operations.

Claim 8

A chip integration structure comprising: a substrate; at least one silicon interposer with one or more power, ground and signal connections to the substrate, the silicon interposer comprising: a plurality of through-silicon vias within a first plane of the interposer in contact with the one or more power, ground and signal connections to the substrate, wherein the through-silicon vias are adapted to serve as power, ground and signal interconnections throughout the first plane such that the through-silicon vias that serve as the power and ground interconnections are greater in at least one of number and size than the through-silicon vias that serve as the signal interconnections so as to support uniform power distribution during low voltage operations; a plurality of lines within a second plane of the interposer in contact with one or more of the through-silicon vias in the first plane, the second plane being adjacent to the first plane, wherein the lines are adapted to serve as power, ground and signal interconnections throughout the second plane such that the lines that serve as the power and ground interconnections are greater in at least one of number and size than the lines that serve as the signal interconnections so as to support uniform power distribution during low voltage operations; and one or more chips, one or more chip stacks or at least one chip in combination with at least one chip stack having one or more power, ground and signal connections to the silicon interposer that are in contact with one or more of the lines within the second plane of the interposer.

Claim 9

A chip integration structure comprising: a substrate; at least one silicon interposer with one or more power, ground and signal connections to the substrate, the silicon interposer comprising: a plurality of through-silicon vias within a first plane of the interposer in contact with the one or more power, ground and signal connections to the substrate, wherein the through-silicon vias are adapted to serve as power, ground and signal interconnections throughout the first plane such that the through-silicon vias that serve as the power and ground interconnections are greater in at least one of number and size than the through-silicon vias that serve as the signal interconnections so as to support uniform power distribution during low voltage operations; a plurality of lines within a second plane of the interposer in contact with one or more of the through-silicon vias in the first plane, the second plane being adjacent to the first plane, wherein the lines are adapted to serve as power, ground and signal interconnections throughout the second plane such that the lines that serve as the power and ground interconnections are greater in at least one of number and size than the lines that serve as the signal interconnections so as to support uniform power distribution during low voltage operations; and one or more chips, one or more chip stacks or at least one chip in combination with at least one chip stack having one or more power, ground and signal connections to the silicon interposer that are in contact with one or more of the lines within the second plane of the interposer.

Claim 10

The chip integration structure of claim 7 , further comprising: a printed wire board having one or more power, ground and signal connections to the substrate.

Claim 11

The chip integration structure of claim 7 , further comprising: at least one decoupling capacitor having one or more power and ground connections to the substrate.

Claim 12

The chip integration structure of claim 8 , further comprising: a package having one or more power, ground and signal connections to both the substrate and the printed wire board.

Claim 13

The chip integration structure of claim 7 , comprising a plurality of the silicon interposers, at least two of which are in a stacked configuration with one another.

Claim 14

The chip integration structure of claim 7 , comprising a plurality of the silicon interposers and a plurality of the chip stacks, wherein each of the chip stacks is located between two of the silicon interposers.

Claim 15

The chip integration structure of claim 7 , comprising a plurality of the silicon interposers and a plurality of the chip stacks, wherein each of the chip stacks is located between two of the silicon interposers, the chip integration structure further comprising: at least one silicon layer between each of the silicon interposers; and one or more through-silicon vias that extend through each silicon layer.

Claim 16

The chip integration structure of claim 13 , wherein the through-silicon vias that extend through each of the silicon layers comprise through-silicon via farms surrounding the chip stacks.

Claim 17

The chip integration structure of claim 7 , comprising at least one chip stack, wherein each chip adjacent to another chip in the stack has power, ground and signal connections to the adjacent chip.

Claim 18

The chip integration structure of claim 7 , comprising a plurality of the silicon interposers and a plurality of the chip stacks, wherein each of the chip stacks is located between two of the silicon interposers, and wherein one or more of the chip stacks comprise memory chip stacks.

Claim 19

The chip integration structure of claim 7 , comprising a plurality of the silicon interposers and a plurality of the chip stacks, wherein each of the chip stacks is located between two of the silicon interposers, the chip integration structure further comprising: at least one processor chip connected to a topmost one of the silicon interposers.

Claim 20

The chip integration structure of claim 17 , further comprising: at least one cooling unit in contact with one of the silicon interposers, the processor chip or one of the chip stacks.

Claim 21

The chip integration structure of claim 18 , wherein the cooling unit is a heat spreader, a cooler, a heat pipe, a cooling fin or a cooling assembly.

Claim 24

The method of claim 20 , further comprising the step of: planing a side of the wafer opposite the insulator layer so as to expose one or more of the through-silicon vias.

Claim 25

The method of claim 20 , further comprising the steps of: etching a plurality of holes in the wafer, each hole corresponding to one of the through-silicon vias; depositing an insulation material on a bottom and sides of each of the holes; and filling the holes with at least one metal to form the through-silicon vias.