Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length

Claim 1

A method of fabricating an enhancement-mode field-effect transistor from a semiconductor body having body material of a first conductivity type, the method comprising: providing a gate electrode above, and vertically separated by a gate dielectric layer from, a portion of the body material intended to be a channel zone for the transistor; and subsequently (a) introducing semiconductor dopant of the first conductivity type into at least the intended channel-zone portion of the body material and (b) introducing semiconductor dopant of a second conductivity type opposite to the first conductivity type into the semiconductor body to form first and second source/drain zones of the second conductivity type laterally separated by the channel zone such that the first source/drain zone comprises a main source/drain portion and a more lightly doped lower source/drain portion underlying, and vertically continuous with, the main source/drain portion, the channel zone having a channel length extending along the gate dielectric layer from either of the source/drain zones to the other of the source/drain zones, the transistor having a threshold voltage which depends on the channel length at a given set of post-layout fabrication process conditions so as to reach a maximum absolute value V TAM at a value L C of the channel length, to be at least 0.03 volt less than V TAM in absolute value when the channel length is approximately 0.3 μm greater than L C , and to be materially decreasing with increasing channel length when the channel length is approximately 1.0 μm greater than L C .

Claim 2

A method of fabricating an enhancement-mode field-effect transistor from a semiconductor body having body material of a first conductivity type, the method comprising: providing a gate electrode above, and vertically separated by a gate dielectric layer from, a portion of the body material intended to be a channel zone for the transistor; and subsequently (a) introducing semiconductor dopant of the first conductivity type into at least the intended channel-zone portion of the body material and (b) introducing semiconductor dopant of a second conductivity type opposite to the first conductivity type into the semiconductor body to form first and second source/drain zones of the second conductivity type laterally separated by the channel zone such that the first source/drain zone comprises a main source/drain portion and a more lightly doped lower source/drain portion underlying, and vertically continuous with, the main source/drain portion, the channel zone having a channel length extending along the gate dielectric layer from either of the source/drain zones to the other of the source/drain zones, the transistor having a threshold voltage which depends on the channel length at a given set of post-layout fabrication process conditions so as to reach a maximum absolute value V TAM at a value L C of the channel length, to be at least 0.03 volt less than V TAM in absolute value when the channel length is approximately 0.3 μm greater than L C , and to be materially decreasing with increasing channel length when the channel length is approximately 1.0 μm greater than L C .

Claim 10

A method of fabricating a structure having a plurality of like-polarity enhancement-mode insulated-gate field-effect transistors whose respective threshold voltages depend on transistor channel length, the method comprising: laying out the transistors to have channel lengths of multiple different values of at least a value L C ; and subsequently forming the transistors substantially simultaneously from a semiconductor body at their respective channel lengths according to a set of fabrication conditions which are substantially identical from transistor to transistor for all such fabrication process conditions that significantly affect the threshold voltages such that the threshold voltages have a group characteristic of reaching a maximum absolute value V TAM when channel length largely equals L C , of being at least 0.03 volt less than V TAM in absolute value when channel length is approximately 0.3 μm greater than L C , and of materially decreasing with increasing channel length when channel length is approximately 1.0 μm greater than L C and such that the semiconductor body has an upper surface along which the channel length of each transistor extends from either of first and second source/drain zones of that transistor to the other of the source/drain zones of that transistor, the first source/drain zone of a specified one of the transistors comprising a main source/drain portion and a more lightly doped lower source/drain portion underlying, and vertically continuous with, the main source/drain portion.

Claim 11

A method of fabricating a structure having a plurality of like-polarity enhancement-mode insulated-gate field-effect transistors whose respective threshold voltages depend on transistor channel length, the method comprising: laying out the transistors to have channel lengths of multiple different values of at least a value L C ; and subsequently forming the transistors substantially simultaneously from a semiconductor body at their respective channel lengths according to a set of fabrication conditions which are substantially identical from transistor to transistor for all such fabrication process conditions that significantly affect the threshold voltages such that the threshold voltages have a group characteristic of reaching a maximum absolute value V TAM when channel length largely equals L C , of being at least 0.03 volt less than V TAM in absolute value when channel length is approximately 0.3 μm greater than L C , and of materially decreasing with increasing channel length when channel length is approximately 1.0 μm greater than L C and such that the semiconductor body has an upper surface along which the channel length of each transistor extends from either of first and second source/drain zones of that transistor to the other of the source/drain zones of that transistor, the first source/drain zone of a specified one of the transistors comprising a main source/drain portion and a more lightly doped lower source/drain portion underlying, and vertically continuous with, the main source/drain portion.

Claim 13

A method comprising: providing a post-layout process for forming a general enhancement-mode insulated-gate field-effect transistor having a threshold voltage that varies with channel length such that, at a given set of post-layout fabrication process conditions, the threshold voltage depends on the transistor's channel length so as to reach a maximum absolute value V TAM at a value L C of the transistor's channel length, to be at least 0.03 volt less than V TAM in absolute value when the transistor's channel length is approximately 0.3 μm greater than L C , and to be materially decreasing with increasing channel length when the channel length is approximately 1.0 μm greater than L C ; laying out a plurality of actual like-polarity enhancement-mode insulated-gate field-effect transistors to have channel lengths of multiple different values of at least L C ; and subsequently forming the actual transistors by substantially utilizing the post-layout process to form the actual transistors substantially simultaneously from a semiconductor body such that the post-layout fabrication process conditions for forming the actual transistors are substantially identical from actual transistor to actual transistor for all such fabrication process conditions that significantly affect transistor threshold voltage and such that the semiconductor body has an upper surface along which the channel length of each actual transistor extends from either of first and second source/drain zones of that transistor to the other of the source/drain zones of that transistor, the first source/drain zone of a specified one of the actual transistors comprising a main source/drain portion and a more lightly doped lower source/drain portion underlying, and vertically continuous with, the main source/drain portion.

Claim 14

A method comprising: providing a post-layout process for forming a general enhancement-mode insulated-gate field-effect transistor having a threshold voltage that varies with channel length such that, at a given set of post-layout fabrication process conditions, the threshold voltage depends on the transistor's channel length so as to reach a maximum absolute value V TAM at a value L C of the transistor's channel length, to be at least 0.03 volt less than V TAM in absolute value when the transistor's channel length is approximately 0.3 μm greater than L C , and to be materially decreasing with increasing channel length when the channel length is approximately 1.0 μm greater than L C ; laying out a plurality of actual like-polarity enhancement-mode insulated-gate field-effect transistors to have channel lengths of multiple different values of at least L C ; and subsequently forming the actual transistors by substantially utilizing the post-layout process to form the actual transistors substantially simultaneously from a semiconductor body such that the post-layout fabrication process conditions for forming the actual transistors are substantially identical from actual transistor to actual transistor for all such fabrication process conditions that significantly affect transistor threshold voltage and such that the semiconductor body has an upper surface along which the channel length of each actual transistor extends from either of first and second source/drain zones of that transistor to the other of the source/drain zones of that transistor, the first source/drain zone of a specified one of the actual transistors comprising a main source/drain portion and a more lightly doped lower source/drain portion underlying, and vertically continuous with, the main source/drain portion.