US7511341B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
SOI device having increased reliability and reduced free floating body effects
Assignee: Micron Technology Inc
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Filing: 2005-09-01
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Granted: 2009-03-31
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Expires: 2025-09-01
Abstract
Abstract The present invention provides a novel method for increasing the amount of deuterium incorporated into trap sites of a transistor device during a deuterium passivation anneal by electrically pre-stressing the fabricated device prior to a deuterium anneal. The method of the present invention equally applies to SOI and CMOS technology. As a result, the incorporation of more deuterium during a deuterium anneal in the process flow reduces the number of undesirable trap sites.
Inventors
- 👤 Chandra Mouli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:01
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/30; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/6704; H10D30/6706; H10D30/6708; H10D86/00; H10D86/01; H10D86/03; H10D86/201; H10P; H10P95/00; H10P95/80; H10P95/94
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
154 words
A transistor comprising: a semiconductor substrate; a buried oxide layer formed within said substrate; a trench isolation region formed within said substrate; a source region; a drain region; a channel region; passivated trap site regions comprising trap sites of at least said buried oxide layer and said channel region, said passivated trap site regions formed by (a) applying different voltages to said source region and said drain region to electrically stress and thereby remove a first passivating species from said trap sites, and (b) after removing said first passivating species from said trap sites, passivating said trap sites with a second passivating species; and a transistor gate formed over said channel region, wherein, due to steps (a) and (b), a percentage of said trap sites passivated by said second passivating species near said drain region is greater than a percentage of said trap sites passivated by said second passivating species near said source region.
Claim 2
Dependent Claim
154 words
A transistor comprising: a semiconductor substrate; a buried oxide layer formed within said substrate; a trench isolation region formed within said substrate; a source region; a drain region; a channel region; passivated trap site regions comprising trap sites of at least said buried oxide layer and said channel region, said passivated trap site regions formed by (a) applying different voltages to said source region and said drain region to electrically stress and thereby remove a first passivating species from said trap sites, and (b) after removing said first passivating species from said trap sites, passivating said trap sites with a second passivating species; and a transistor gate formed over said channel region, wherein, due to steps (a) and (b), a percentage of said trap sites passivated by said second passivating species near said drain region is greater than a percentage of said trap sites passivated by said second passivating species near said source region.
Claim 3
Dependent Claim
14 words
The transistor of claim 1 , wherein said second passivating species are deuterium atoms.
Claim 4
Dependent Claim
50 words
The transistor of claim 1 , wherein said passivated trap site regions comprise first, second, and third trap site regions, said buried oxide layer comprises said first trap site region, said trench isolation region comprises said second trap site region, and said channel region comprises said third trap site region.
Claim 5
Dependent Claim
36 words
The transistor of claim 1 , wherein step (a) further comprises: applying an operational supply voltage of the transistor Vcc to the drain region; and applying a gate voltage of about Vcc/2 to the transistor gate.
Claim 6
Dependent Claim
21 words
The transistor of claim 1 3 , wherein said second trap site region is located along a trench isolation region sidewall.
Claim 7
Dependent Claim
25 words
The transistor of claim 1 3 , wherein said second trap site region is located between said trench isolation region and said buried oxide layer.
Claim 8
Dependent Claim
23 words
The transistor of claim 3 , wherein said second trap site region is located between said trench isolation region and said channel region.
Claim 9
Dependent Claim
22 words
The transistor of claim 3 , wherein said third trap site region is located between said channel region and said transistor gate.
Claim 10
Dependent Claim
23 words
The transistor of claim 3 , wherein said first trap site region is located between said buried oxide layer and said channel region.
Claim 11
Dependent Claim
141 words
A transistor comprising: a source region; a drain region; a channel region; a multi-layer gate formed over a semiconductor substrate, wherein said multi-layer gate comprises an insulating layer and at least one conductive layer; an oxide layer formed within said substrate; at least one trench isolation region; and at least one electrically pre-stressed region comprising trap sites, said electrically pre-stressed region formed by (a) applying an electrical current from said source region to said drain region to remove hydrogen atoms from said trap sites, and (b) immediately re-passivating said trap sites with a passivating species more resistant to hot carriers than said hydrogen atoms, wherein steps (a) and (b) cause portions of said electrically pre-stressed region near said drain region to have a higher concentration of said re-passivated trap sites than portions of said electrically pre-stressed region near said source region.
Claim 12
Dependent Claim
141 words
A transistor comprising: a source region; a drain region; a channel region; a multi-layer gate formed over a semiconductor substrate, wherein said multi-layer gate comprises an insulating layer and at least one conductive layer; an oxide layer formed within said substrate; at least one trench isolation region; and at least one electrically pre-stressed region comprising trap sites, said electrically pre-stressed region formed by (a) applying an electrical current from said source region to said drain region to remove hydrogen atoms from said trap sites, and (b) immediately re-passivating said trap sites with a passivating species more resistant to hot carriers than said hydrogen atoms, wherein steps (a) and (b) cause portions of said electrically pre-stressed region near said drain region to have a higher concentration of said re-passivated trap sites than portions of said electrically pre-stressed region near said source region.
Claim 13
Dependent Claim
16 words
The transistor of claim 10 , wherein said passivating species is at least one deuterium atom.
Claim 14
Dependent Claim
23 words
The transistor of claim 10 , wherein said electrically pre- stressed stressed region has been electrically stressed at less than 650 ° C.
Claim 15
Dependent Claim
23 words
The semiconductor device of claim 10 , wherein said electrically pre-stressed transistor has been electrically stressed under peak substrate conditions of said transistor.
Claim 16
Dependent Claim
33 words
The transistor of claim 13 , wherein said electrically pre- stressed transistor has been electrically stressed by a gate voltage substantially equal to Vd/2, where Vd is a drain voltage of said transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2012-03-30 | 2012-09-29 | 2013-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2016-03-30 | 2016-09-29 | 2017-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2020-03-30 | 2020-09-29 | 2021-03-31 | $7700.00 | Window Closed / Lapsed |