Deuterium treatment of semiconductor devices

Claim 2

1 . A process for treating a semiconductor device including a semiconductor region and an insulating layer having an interface with the semiconductor region, comprising the steps of annealing said semiconductor device during manufacture thereof, in an ambient including deuterium wherein said deuterium has a partial pressure in excess of atmospheric pressure, to form a concentration of deuterium at the interface between said semiconductor region and said insulating layer region effective to substantially reduce degradation of said device associated with hot carrier stress.

Claim 3

2 . A process according to claim 1 , wherein said deuterium partial pressure is between about 2 atmospheres and 15 atmospheres and the annealing is carried out at a temperature between about 150° C. and 600° C.

Claim 4

3 . A process according to claim 2 , wherein the annealing process is carried out for a period in excess of 5 minutes.

Claim 5

4 . A process according to claim 3 , wherein the annealing period is between 30 minutes and 3 hours.

Claim 6

5 . A process for treating a semiconductor device including a semiconductor region and an insulating layer having an interface with the semiconductor region, comprising the steps of exposing said semiconductor device during manufacture thereof to an ambient including deuterium wherein said deuterium has a partial pressure between about 2 atmospheres to about 15 atmospheres, at a temperature above about 150° C. to form a concentration of deuterium greater than 10 16 atoms/cc at the interface between said semiconductor region and said insulating layer.

Claim 7

5 . A process for treating a semiconductor device including a semiconductor region and an insulating layer having an interface with the semiconductor region, comprising the steps of exposing said semiconductor device during manufacture thereof to an ambient including deuterium wherein said deuterium has a partial pressure between about 2 atmospheres to about 15 atmospheres, at a temperature above about 150° C. to form a concentration of deuterium greater than 10 16 atoms/cc at the interface between said semiconductor region and said insulating layer.

Claim 8

6 . A process for treating a semiconductor device including a semiconductor region and an insulating layer having an interface with the semiconductor region, comprising the steps of annealing said semiconductor device during manufacture thereof in an ambient including deuterium wherein said deuterium has a partial pressure in excess of atmospheric pressure up to about 10 atmospheres, at a temperature above about 350° C. to form a concentration of deuterium at the interface between said semiconductor region and said insulating layer.

Claim 9

6 . A process for treating a semiconductor device including a semiconductor region and an insulating layer having an interface with the semiconductor region, comprising the steps of annealing said semiconductor device during manufacture thereof in an ambient including deuterium wherein said deuterium has a partial pressure in excess of atmospheric pressure up to about 10 atmospheres, at a temperature above about 350° C. to form a concentration of deuterium at the interface between said semiconductor region and said insulating layer.

Claim 10

7 . A process according to claim 6 , wherein said deuterium partial pressure is between about 2 atmospheres and about 6 atmospheres.

Claim 11

8 . A process according to claim 6 , wherein said temperature is in the approximate range 350° C. to 450° C.

Claim 12

9 . A process according to claim 6 , wherein said annealing is for a period of about 1-3 hours.

Claim 13

10 . A process according to claim 6 , wherein said annealing treatment is the final thermal processing step in the manufacturing process for the device.

Claim 14

11 . A process for treating a semiconductor device including at least one insulating layer overlying a semiconductor region, comprising the steps of exposing said semiconductor device during manufacture thereof to an ambient including deuterium wherein said deuterium has a partial pressure in excess of atmospheric pressure, at a temperature above about 300° C. to form a concentration of deuterium in the insulating layer of at least 10 18 atoms/cc.

Claim 15

11 . A process for treating a semiconductor device including at least one insulating layer overlying a semiconductor region, comprising the steps of exposing said semiconductor device during manufacture thereof to an ambient including deuterium wherein said deuterium has a partial pressure in excess of atmospheric pressure, at a temperature above about 300° C. to form a concentration of deuterium in the insulating layer of at least 10 18 atoms/cc.

Claim 16

12 . A process for treating an insulated gate field effect transistor device during manufacture thereof to form a concentration of deuterium at an interface between a gate insulator and a channel region of said device, comprising annealing the device in a superatmospheric pressure deuterium ambient at a temperature in the range 300° C. to 600° C. for a time sufficient to provide a deuterium concentration of at least 10 18 atoms/cc at said interface.

Claim 17

12 . A process for treating an insulated gate field effect transistor device during manufacture thereof to form a concentration of deuterium at an interface between a gate insulator and a channel region of said device, comprising annealing the device in a superatmospheric pressure deuterium ambient at a temperature in the range 300° C. to 600° C. for a time sufficient to provide a deuterium concentration of at least 10 18 atoms/cc at said interface.

Claim 18

13 . A process according to claim 12 , wherein said deuterium partial pressure is between about 2 atmospheres and about 6 atmospheres.

Claim 19

14 . A process according to claim 12 , wherein said temperature is in the approximate range 350° C. to 450° C.

Claim 20

15 . A process according to claim 12 , wherein said annealing is for a period of about 1-3 hours.

Claim 21

16 . A process according to claim 12 , wherein said annealing treatment is the final thermal processing step in the manufacturing process for the device.

Claim 22

17 . A process according to claim 12 , wherein said annealing treatment is carried out contact formation and interconnect metallization.

Claim 23

18 . A process according to claim 12 , wherein said deuterium concentration is in the range 10 18 to 10 21 atoms/cc.

Claim 24

19 . A process for treating an insulated gate field effect transistor device including a channel region extending between source and drain regions, an insulating layer forming an interface with said channel region, and contacts to said source and drain regions and on said gate insulator layer, comprising, subsequent to formation of said source, drain and gate contacts, annealing the device in an ambient including deuterium at a partial pressure between about 2 and 10 atmospheres, at a temperature between about 300° C. and 600° C. for a period between about 30 minutes and three hours, to form a concentration of deuterium at said interface region.

Claim 25

19 . A process for treating an insulated gate field effect transistor device including a channel region extending between source and drain regions, an insulating layer forming an interface with said channel region, and contacts to said source and drain regions and on said gate insulator layer, comprising, subsequent to formation of said source, drain and gate contacts, annealing the device in an ambient including deuterium at a partial pressure between about 2 and 10 atmospheres, at a temperature between about 300° C. and 600° C. for a period between about 30 minutes and three hours, to form a concentration of deuterium at said interface region.

Claim 26

20 . A process for treating an insulated gate field effect transistor device including a channel region extending between source and drain regions, an insulating layer forming an interface with said channel region, and contacts to said source and drain regions and on said gate insulator layer, comprising, subsequent to formation of said source, drain and gate contacts, annealing the device in an ambient including deuterium at a partial pressure between about 2 and 6 atmospheres, at a temperature between about 350° C. and 450° C. to form a concentration of deuterium at said interface region effective to substantially reduce degradation of said device associated with hot carrier stress.

Claim 27

20 . A process for treating an insulated gate field effect transistor device including a channel region extending between source and drain regions, an insulating layer forming an interface with said channel region, and contacts to said source and drain regions and on said gate insulator layer, comprising, subsequent to formation of said source, drain and gate contacts, annealing the device in an ambient including deuterium at a partial pressure between about 2 and 6 atmospheres, at a temperature between about 350° C. and 450° C. to form a concentration of deuterium at said interface region effective to substantially reduce degradation of said device associated with hot carrier stress.

Claim 28

21 . A process according to claim 20 , wherein said annealing step comprises the final thermal processing step in manufacture of the device.

Claim 29

22 . A process according to claim 20 , wherein the annealing ambient is 100% deuterium.

Claim 30

23 . A process for treating an insulated gate field effect transistor device including a channel region extending between source and drain regions, an insulating layer forming an interface with said channel region, contacts to said source and drain regions and on said gate insulator layer, insulating sidewall spacers adjacent to said gate contact, and an insulating barrier cap over said gate contact, comprising, subsequent to formation of said source, drain and gate contacts, of said sidewall spacers and of said insulating barrier cap, annealing the device in an ambient including deuterium at a partial pressure between about 2 and 10 atmospheres, at a temperature between about 300° C. and 600° C. for a period between from 30 minutes to about three hours, to form a concentration of deuterium at said interface region effective to substantially reduce degradation of said device associated with hot carrier stress.

Claim 31

23 . A process for treating an insulated gate field effect transistor device including a channel region extending between source and drain regions, an insulating layer forming an interface with said channel region, contacts to said source and drain regions and on said gate insulator layer, insulating sidewall spacers adjacent to said gate contact, and an insulating barrier cap over said gate contact, comprising, subsequent to formation of said source, drain and gate contacts, of said sidewall spacers and of said insulating barrier cap, annealing the device in an ambient including deuterium at a partial pressure between about 2 and 10 atmospheres, at a temperature between about 300° C. and 600° C. for a period between from 30 minutes to about three hours, to form a concentration of deuterium at said interface region effective to substantially reduce degradation of said device associated with hot carrier stress.

Claim 32

24 . A process according to claim 23 , wherein said deuterium concentration is in the range 10 18 to 10 21 atoms/cc.

Claim 33

25 . A semiconductor device including a semiconductor region and an insulating layer having an interface with the semiconductor region, including a concentration of deuterium in excess of about 10 18 atoms/cc at the interface between said semiconductor region and said insulating layer region, said deuterium concentration effective to substantially reduce degradation of said device associated with hot carrier stress.

Claim 34

25 . A semiconductor device including a semiconductor region and an insulating layer having an interface with the semiconductor region, including a concentration of deuterium in excess of about 10 18 atoms/cc at the interface between said semiconductor region and said insulating layer region, said deuterium concentration effective to substantially reduce degradation of said device associated with hot carrier stress.

Claim 35

26 . A semiconductor device according to claim 25 , wherein said deuterium concentration is in the range 10 18 to 10 21 atoms/cc.

Claim 36

27 . An insulated gate field effect transistor device including a channel region extending between source and drain regions, an insulating layer forming an interface with said channel region, and contacts to said source and drain regions and on said gate insulator layer, including a concentration of deuterium in excess of about 10 18 atoms/cc at said interface region effective to substantially reduce degradation of said device associated with hot carrier stress.

Claim 37

27 . An insulated gate field effect transistor device including a channel region extending between source and drain regions, an insulating layer forming an interface with said channel region, and contacts to said source and drain regions and on said gate insulator layer, including a concentration of deuterium in excess of about 10 18 atoms/cc at said interface region effective to substantially reduce degradation of said device associated with hot carrier stress.

Claim 38

28 . An insulated gate field effect device according to claim 27 , wherein said deuterium concentration is in the range 10 18 to 10 21 atoms/cc.

Claim 39

29 A semiconductor device including a semiconductor region and an insulating layer having an interface with conductive layer, including a concentration of deuterium in excess of about 10 18 atoms/cc in said insulating layer.

Claim 40

29 A semiconductor device including a semiconductor region and an insulating layer having an interface with conductive layer, including a concentration of deuterium in excess of about 10 18 atoms/cc in said insulating layer.

Claim 41

30 . A semiconductor device according to claim 29 , wherein said deuterium concentration is in the range 10 18 to 10 21 atoms/cc.