US7187742B1
Expired / Lapsed
US
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Synchronized multi-output digital clock manager
Assignee: Xilinx Inc
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Filing: 2000-10-06
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Granted: 2007-03-06
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Expires: 2020-10-06
Abstract
Abstract A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchronized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a delay lock loop and a digital frequency synthesizer. The delay lock loop generates a synchronizing clock signal that is provided to the digital frequency synthesizer. The output clock signal lags the synchronizing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matching the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal.
Inventors
- 👤 John D. Logue
- 👤 Andrew K. Percey
- 👤 F. Erich Goetting
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:07
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/07; G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/0818
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
136 words
A digital clock manager having a reference input terminal, a skew input terminal, an output terminal, and a frequency adjusted output terminal, the digital clock manager comprising: a delay lock loop (DLL) coupled to the reference input terminal, the skew input terminal, and the output terminal, wherein the delay lock loop generates an output clock signal at the output terminal; wherein the delay lock loop comprises a DLL output circuit having a DLL output delay; and a digital frequency synthesizer (DFS), having a variable oscillator, coupled to receive a clock signal generated by the delay lock loop and the frequency adjusted output terminal, wherein the digital frequency synthesizer generates a frequency adjusted clock signal at the frequency adjusted output terminal and wherein the frequency adjusted clock signal is synchronized with the output clock signal during concurrences.
Claim 2
Dependent Claim
136 words
A digital clock manager having a reference input terminal, a skew input terminal, an output terminal, and a frequency adjusted output terminal, the digital clock manager comprising: a delay lock loop (DLL) coupled to the reference input terminal, the skew input terminal, and the output terminal, wherein the delay lock loop generates an output clock signal at the output terminal; wherein the delay lock loop comprises a DLL output circuit having a DLL output delay; and a digital frequency synthesizer (DFS), having a variable oscillator, coupled to receive a clock signal generated by the delay lock loop and the frequency adjusted output terminal, wherein the digital frequency synthesizer generates a frequency adjusted clock signal at the frequency adjusted output terminal and wherein the frequency adjusted clock signal is synchronized with the output clock signal during concurrences.
Claim 3
Dependent Claim
33 words
The digital clock manager of claim 1 , wherein the delay lock loop synchronizes a reference clock signal on the reference input terminal with a skewed clock signal on the skew input terminal.
Claim 4
Dependent Claim
23 words
The digital clock manager of claim 1 , wherein the digital frequency synthesizer comprises a DFS output circuit having a DFS output delay.
Claim 5
Dependent Claim
24 words
The digital clock manager of claim 1 , further comprising a variable delay circuit coupled between the delay lock loop and the output terminal.
Claim 6
Dependent Claim
26 words
The digital clock manager of claim 1 , further comprising a variable delay circuit coupled between the digital frequency synthesizer and the frequency adjusted output terminal.
Claim 7
Dependent Claim
26 words
The digital clock manager of claim 1 , wherein the digital frequency synthesizer performs a frequency search while the delay lock loop is performing lock acquisition.
Claim 8
Dependent Claim
21 words
The digital clock manager of claim 3 , wherein the DLL output delay is substantially equal to the DFS output delay.
Claim 9
Dependent Claim
29 words
The digital clock manager of claim 3 , wherein the DLL output circuit comprises a plurality of components and the DFS output circuit comprises the same plurality of components.
Claim 10
Dependent Claim
130 words
A digital clock manager having a reference input terminal, a skew input terminal, an output terminal, and a frequency adjusted output terminal, the digital clock manager comprising: a delay lock loop (DLL) coupled to the reference input terminal, the skew input terminal, and the output terminal, wherein the delay lock loop generates an output clock signal at the output terminal; wherein the delay lock loop comprises a DLL output circuit having a DLL output delay; and a digital frequency synthesizer (DFS), having a variable oscillator, coupled to the delay lock loop and the frequency adjusted output terminal, wherein the digital frequency synthesizer generates a frequency adjusted clock signal at the frequency adjusted output terminal and wherein the frequency adjusted clock signal is synchronized with the output clock signal during concurrences.
Claim 11
Dependent Claim
130 words
A digital clock manager having a reference input terminal, a skew input terminal, an output terminal, and a frequency adjusted output terminal, the digital clock manager comprising: a delay lock loop (DLL) coupled to the reference input terminal, the skew input terminal, and the output terminal, wherein the delay lock loop generates an output clock signal at the output terminal; wherein the delay lock loop comprises a DLL output circuit having a DLL output delay; and a digital frequency synthesizer (DFS), having a variable oscillator, coupled to the delay lock loop and the frequency adjusted output terminal, wherein the digital frequency synthesizer generates a frequency adjusted clock signal at the frequency adjusted output terminal and wherein the frequency adjusted clock signal is synchronized with the output clock signal during concurrences.
Claim 12
Dependent Claim
143 words
A digital clock manager having a reference input terminal, a skew input terminal, an output terminal, and a frequency adjusted output terminal, the digital clock manager comprising: a delay lock loop (DLL) coupled to the reference input terminal, the skew input terminal, and the output terminal, wherein the delay lock loop generates an output clock signal at the output terminal; wherein the delay lock loop comprises a DLL output circuit having a DLL output delay; a multiplexer having a first input terminal coupled to the reference input terminal, a second input terminal coupled to the delay lock loop, and an output terminal; and a digital frequency synthesizer (DFS), having a variable oscillator, coupled to the output terminal of the multiplexer and the frequency adjusted output terminal, wherein the digital frequency synthesizer generates a frequency adjusted clock signal at the frequency adjusted output terminal.
Claim 13
Dependent Claim
143 words
A digital clock manager having a reference input terminal, a skew input terminal, an output terminal, and a frequency adjusted output terminal, the digital clock manager comprising: a delay lock loop (DLL) coupled to the reference input terminal, the skew input terminal, and the output terminal, wherein the delay lock loop generates an output clock signal at the output terminal; wherein the delay lock loop comprises a DLL output circuit having a DLL output delay; a multiplexer having a first input terminal coupled to the reference input terminal, a second input terminal coupled to the delay lock loop, and an output terminal; and a digital frequency synthesizer (DFS), having a variable oscillator, coupled to the output terminal of the multiplexer and the frequency adjusted output terminal, wherein the digital frequency synthesizer generates a frequency adjusted clock signal at the frequency adjusted output terminal.
Claim 14
Dependent Claim
29 words
The digital clock manager of claim 10 , wherein the delay lock loop is configured to provide a synchronizing clock signal to the second input terminal of the multiplexer.
Claim 15
Dependent Claim
32 words
The digital clock manager of claim 11 , wherein the digital frequency synthesizer is configured to perform a frequency search phase using a reference clock signal provided to the reference input terminal.
Claim 16
Dependent Claim
28 words
The digital clock manager of claim 12 , wherein the digital frequency synthesizer is configured to provide a frequency adjusted clock signal based on the synchronizing clock signal.
Claim 17
Dependent Claim
130 words
A digital clock manager having a reference input terminal, a skew input terminal, an output terminal, and a frequency adjusted output terminal, the digital clock manager comprising: a delay lock loop (DLL) coupled to the reference input terminal, the skew input terminal, and the output terminal, wherein the delay lock loop generates an output clock signal at the output terminal; a digital frequency synthesizer (DFS), having a variable oscillator, coupled to the delay lock loop and the frequency adjusted output terminal, wherein the digital frequency synthesizer generates a frequency adjusted clock signal at the frequency adjusted output terminal; and wherein the delay lock loop drives a synchronizing clock signal to the digital frequency synthesizer and wherein the frequency adjusted clock signal is synchronized with the output clock signal during concurrences.
Claim 18
Dependent Claim
130 words
A digital clock manager having a reference input terminal, a skew input terminal, an output terminal, and a frequency adjusted output terminal, the digital clock manager comprising: a delay lock loop (DLL) coupled to the reference input terminal, the skew input terminal, and the output terminal, wherein the delay lock loop generates an output clock signal at the output terminal; a digital frequency synthesizer (DFS), having a variable oscillator, coupled to the delay lock loop and the frequency adjusted output terminal, wherein the digital frequency synthesizer generates a frequency adjusted clock signal at the frequency adjusted output terminal; and wherein the delay lock loop drives a synchronizing clock signal to the digital frequency synthesizer and wherein the frequency adjusted clock signal is synchronized with the output clock signal during concurrences.
Claim 19
Dependent Claim
40 words
The digital clock manager of claim 14 , wherein the delay lock loop is configured to generate an output clock signal on the output terminal, wherein the output clock signal lags the synchronizing clock signal by a DLL output delay.
Claim 20
Dependent Claim
36 words
The digital clock manager of claim 15 , wherein an active edge of the frequency adjusted clock signal lags an active edge of the synchronizing clock signal by a DFS output delay during a concurrence period.
Claim 21
Dependent Claim
21 words
The digital clock manager of claim 16 , wherein the DLL output delay is substantially equal to the DFS output delay.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-03-05 | 2010-09-04 | 2011-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-03-05 | 2014-09-04 | 2015-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-03-05 | 2018-09-04 | 2019-03-06 | $7700.00 | Window Closed / Lapsed |