US5511100A
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US
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Method and apparatus for performing frequency detection
Assignee: Motorola Solutions Inc
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Filing: 1993-12-13
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Granted: 1996-04-23
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Expires: 2013-12-13
Abstract
Abstract A method and apparatus for performing frequency detection in an all digital phase lock loop (10). Frequency detection is accomplished using a frequency detector (11), coupled to an digitally controlled oscillator (DCO 16). The frequency detector (11) forces phase alignment of a reference clock signal to the DCO (16) output and then counts the number the DCO (16) output pulses occurring during a reference clock period. The reference clock signal enables the DCO (16) on one signal transition and detects the presence of an oscillator counter (52) output on the same reference clock signal transition, but one reference clock period later. A synchronizer (49) is used to pass the counter (52) output to ensure no metastability. The DCO (16) is then disabled to allow frequency adjustments to occur via other circuitry.
Inventors
- 👤 James R. Lundberg
- 👤 Charles E. Nuckolls
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:33
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/113; G; G01; G01R; G01R23/00; G01R23/02; G01R23/10; H03D; H03D13/00; H03D13/001; H03L7/107; H03L2207/00; H03L2207/50; H03L7/085; H03L7/089; H03L7/099; H03L7/0991
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
341 words
In a system having a clock generator for generating a reference clock signal and an oscillator for performing frequency synthesis, a frequency detector for comparing a frequency of the reference clock signal to an oscillator output signal, said frequency detector comprising: counter circuitry for serially counting a number of signal transitions of said oscillator output signal, relative to a predefined number of transitions of said reference clock signal, and for providing a count output signal indicating whether the number of signal transitions of said oscillator output signal is less than or not less than a target number, said counter circuitry comprising; a first counter having an input for receiving said oscillator output signal and an output for providing said count output signal indicating whether the number of signal transitions of said oscillator output, relative to a predefined number of transitions of said reference clock signal, is less than or not less than a target number; and a reference clock counter for counting said predefined number of transitions of said reference clock signal, and for providing a reset signal to reset said first counter to an initial value; synchronization circuitry, coupled to said counter circuitry, for receiving said count output signal and for generating, during a predefined reference clock interval, a first control signal when said count output signal is less than said target number, or a second control signal when said count output signal is not less than said target; a delay circuit, coupled to said enable circuitry, for matching a delay inherent in the counter circuitry with a propagation delay relative to the reference clock signal; and enable circuitry, coupled to said oscillator and said counter circuitry, for receiving the reference clock signal and a start signal, and providing an enable signal, in response thereto, to force said oscillator to generate said oscillator output signal synchronously with the reference clock signal, said enable circuitry resetting said first counter in response to receiving said reset signal from said reference clock counter, and resetting said oscillator during said predefined reference clock interval.
Claim 2
Dependent Claim
341 words
In a system having a clock generator for generating a reference clock signal and an oscillator for performing frequency synthesis, a frequency detector for comparing a frequency of the reference clock signal to an oscillator output signal, said frequency detector comprising: counter circuitry for serially counting a number of signal transitions of said oscillator output signal, relative to a predefined number of transitions of said reference clock signal, and for providing a count output signal indicating whether the number of signal transitions of said oscillator output signal is less than or not less than a target number, said counter circuitry comprising; a first counter having an input for receiving said oscillator output signal and an output for providing said count output signal indicating whether the number of signal transitions of said oscillator output, relative to a predefined number of transitions of said reference clock signal, is less than or not less than a target number; and a reference clock counter for counting said predefined number of transitions of said reference clock signal, and for providing a reset signal to reset said first counter to an initial value; synchronization circuitry, coupled to said counter circuitry, for receiving said count output signal and for generating, during a predefined reference clock interval, a first control signal when said count output signal is less than said target number, or a second control signal when said count output signal is not less than said target; a delay circuit, coupled to said enable circuitry, for matching a delay inherent in the counter circuitry with a propagation delay relative to the reference clock signal; and enable circuitry, coupled to said oscillator and said counter circuitry, for receiving the reference clock signal and a start signal, and providing an enable signal, in response thereto, to force said oscillator to generate said oscillator output signal synchronously with the reference clock signal, said enable circuitry resetting said first counter in response to receiving said reset signal from said reference clock counter, and resetting said oscillator during said predefined reference clock interval.
Claim 3
Dependent Claim
80 words
The system of claim 1 wherein said enable circuitry comprises: a first logic portion having an input for receiving said reference clock signal and a first oscillator control signal, and an output for enabling said oscillator to generate said oscillator output signal, synchronously with said reference clock signal, and for resetting said counter circuitry; and a second logic portion having an input for receiving said reset signal provided by said reference clock counter, and an output for disabling said oscillator.
Claim 4
Dependent Claim
338 words
In a system having a clock generator for generating a reference clock signal and an oscillator for performing frequency synthesis, a frequency detector for comparing a frequency of the reference clock signal to an oscillator output signal, said frequency detector comprising: enable circuitry, coupled to said oscillator, for receiving the reference clock signal and a start signal, and providing an enable signal, in response thereto., to force said oscillator to generate said oscillator output signal synchronously with the reference clock signal; counter circuitry for serially counting a number of signal transitions of said oscillator output signal, relative to a predefined number of transitions of said reference clock signal, and for providing a count output signal indicating the number of signal transitions of said oscillator output signal,, a first counter for serially counting a number of signal transitions of said oscillator output signal, relative to a predefined number of transitions of said reference clock signal, said first counter having an input for receiving said oscillator output signal and an output for providing said count output signal indicating whether the number of signal transitions of said oscillator output., relative to a predefined number of transitions of said reference clock signal, is less than or not less than a target number; and a reference clock counter for counting said predefined number of transitions of said reference clock signal, and for providing a reset signal to reset said first counter to an initial value; synchronization circuitry, coupled to said first counter and the enable circuitry, for receiving said count output signal and for generating, during a predefined reference clock interval, a set of binary signals indicating whether said number of signal transitions of said oscillator output signal is at least a predefined integer number, said enable circuitry resetting said first counter, said reference clock counter and said oscillator during said predefined reference clock interval; and a delay circuit, coupled to said enable circuitry, for matching a delay inherent in the first counter with a propagation delay relative to the reference clock signal.
Claim 5
Dependent Claim
338 words
In a system having a clock generator for generating a reference clock signal and an oscillator for performing frequency synthesis, a frequency detector for comparing a frequency of the reference clock signal to an oscillator output signal, said frequency detector comprising: enable circuitry, coupled to said oscillator, for receiving the reference clock signal and a start signal, and providing an enable signal, in response thereto., to force said oscillator to generate said oscillator output signal synchronously with the reference clock signal; counter circuitry for serially counting a number of signal transitions of said oscillator output signal, relative to a predefined number of transitions of said reference clock signal, and for providing a count output signal indicating the number of signal transitions of said oscillator output signal,, a first counter for serially counting a number of signal transitions of said oscillator output signal, relative to a predefined number of transitions of said reference clock signal, said first counter having an input for receiving said oscillator output signal and an output for providing said count output signal indicating whether the number of signal transitions of said oscillator output., relative to a predefined number of transitions of said reference clock signal, is less than or not less than a target number; and a reference clock counter for counting said predefined number of transitions of said reference clock signal, and for providing a reset signal to reset said first counter to an initial value; synchronization circuitry, coupled to said first counter and the enable circuitry, for receiving said count output signal and for generating, during a predefined reference clock interval, a set of binary signals indicating whether said number of signal transitions of said oscillator output signal is at least a predefined integer number, said enable circuitry resetting said first counter, said reference clock counter and said oscillator during said predefined reference clock interval; and a delay circuit, coupled to said enable circuitry, for matching a delay inherent in the first counter with a propagation delay relative to the reference clock signal.
Claim 6
Dependent Claim
80 words
The system of claim 3 wherein said enable circuitry comprises: a first logic portion having an input for receiving said reference clock signal and a first oscillator control signal, and an output for enabling said oscillator to generate said oscillator output signal, synchronously with said reference clock signal, and for resetting said counter circuitry; and a second logic portion having an input for receiving said reset signal provided by said reference clock counter, and an output for disabling said oscillator.
Claim 7
Dependent Claim
232 words
In a system having a clock generator for generating a reference clock signal, an oscillator for performing frequency synthesis, a synchronization circuitry coupled to a counter, and enable logic circuitry coupled to said synchronization circuitry and said oscillator, a method for performing frequency detection comprising the steps of: forcing phase alignment of said oscillator output signal to said reference clock signal by enabling, via said enable logic circuitry said oscillator to generate said oscillator output signal , synchronously with the reference clock signal; serially counting, via said counter, a number of signal transitions of said oscillator output signal, relative to a predefined number of transitions of said reference clock signal, and providing a count output signal indicating whether the number of signal transitions of said oscillator output signal is less than or not less than a target number; matching, via said enable logic circuitry, a delay inherent in the counter and the enable logic circuitry with a propagation delay relative to the reference clock signal; receiving, via said synchronization circuitry, said count output signal and generating, during a predefined reference clock interval, a first control signal, when said count output signal is less than said target number, or a second control signal when said count output signal is not less than said target; and resetting, via said enable logic circuitry, said counter circuitry and said oscillator during said predefined reference clock interval.
Claim 8
Dependent Claim
232 words
In a system having a clock generator for generating a reference clock signal, an oscillator for performing frequency synthesis, a synchronization circuitry coupled to a counter, and enable logic circuitry coupled to said synchronization circuitry and said oscillator, a method for performing frequency detection comprising the steps of: forcing phase alignment of said oscillator output signal to said reference clock signal by enabling, via said enable logic circuitry said oscillator to generate said oscillator output signal , synchronously with the reference clock signal; serially counting, via said counter, a number of signal transitions of said oscillator output signal, relative to a predefined number of transitions of said reference clock signal, and providing a count output signal indicating whether the number of signal transitions of said oscillator output signal is less than or not less than a target number; matching, via said enable logic circuitry, a delay inherent in the counter and the enable logic circuitry with a propagation delay relative to the reference clock signal; receiving, via said synchronization circuitry, said count output signal and generating, during a predefined reference clock interval, a first control signal, when said count output signal is less than said target number, or a second control signal when said count output signal is not less than said target; and resetting, via said enable logic circuitry, said counter circuitry and said oscillator during said predefined reference clock interval.
Claim 9
Dependent Claim
48 words
The method of claim 5 wherein the step of enabling said oscillator to generate an oscillator output signal, synchronously with the reference clock signal comprises the step of receiving said reference clock signal and a first oscillator control signal, and providing an oscillator enable signal in response thereto.
Claim 10
Dependent Claim
118 words
The method of claim 5 wherein the step of serially counting a number of signal transitions of said oscillator output signal, relative to a predefined number of transitions of said reference clock signal, and providing a count output signal indicating whether the number of signal transitions of said oscillator output signal is less than or not less than a target number comprises the steps of: counting said predefined number of transitions of said reference clock signal; and receiving, via said counter, said oscillator output signal and said reference clock signal, and providing said count output signal indicating the number of signal transitions of said oscillator output, relative to said predefined number of transitions of said reference clock signal.
Claim 11
Dependent Claim
37 words
The system of claim 1 wherein said delay circuit matches said delay inherent in the counter circuitry with the propogation delay relative to the reference clock signal and provides a delay clock signal to the synchronization circuitry.
Claim 12
Dependent Claim
20 words
The system of claim 1 wherein said first counter comprises a serial shift register clocked by said oscillator output signal.
Claim 13
Independent Claim
12 words
The system of 1 wherein said synchronization circuitry comprises a two-stage synchronizer.
Claim 14
Independent Claim
12 words
The system of 1 wherein said synchronization circuitry comprises a two-stage synchronizer.
Claim 15
Dependent Claim
38 words
The system of claim 3 wherein said delay circuit matches said delay inherent in the counter circuitry with the propogation delay relative to the reference clock signal and provides a delay clock signal to the synchronization circuitry .
Claim 16
Dependent Claim
20 words
The system of claim 3 wherein said first counter comprises a serial shift register clocked by said oscillator output signal.
Claim 17
Independent Claim
12 words
The system of 3 wherein said synchronization circuitry comprises a two-stage synchronizer.
Claim 18
Independent Claim
12 words
The system of 3 wherein said synchronization circuitry comprises a two-stage synchronizer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-23 | 1999-10-23 | 2000-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-23 | 2003-10-23 | 2004-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-23 | 2007-10-23 | 2008-04-23 | $7700.00 | Window Closed / Lapsed |