Semiconductor device having timing stabilization circuit with overflow detection function

Claim 2

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing stabilization circuit which generates a plurality of phase-adjusted clock signals by adjusting a timing of said internal clock signal by delaying said internal clock signal by a plurality of variable-delay circuits, each of at least two variable-delay circuits of said plurality of variable delay circuits being controlled separately by a corresponding one of independent delay-control circuits such that the phase-adjusted clock signals have phases independent of each other; and an overflow-detection circuit which detects overflow when at least one of said plurality of variable-delay circuits has a delay exceeding the adjustable delay range, said overflow-detection circuit being connected to each of said independent delay-control circuits.

Claim 3

The semiconductor device as claimed in claim 1 , wherein said overflow-detection circuit detects overflow at an instance when said delay is set to an upper end of said adjustable delay range in said at least one of said plurality of variable-delay circuits or at an instance when said delay is attempted to be increased from said upper end in said at least one of said plurality of variable-delay circuits.

Claim 4

The semiconductor device as claimed in claim 1 , further comprising an output circuit which outputs an overflow-detection signal to an exterior of said semiconductor device when said overflow-detection circuit detects overflow.

Claim 5

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing stabilization circuit which generates a plurality of phase-adjusted clock signals by adjusting a timing of said internal clock signal by delaying said internal clock signal by a plurality of variable-delay circuits, each of at least two variable-delay circuits of said plurality of variable delay circuits being controlled separately by a corresponding one of independent delay-control circuits such that the phase-adjusted clock signals have phases independent of each other, wherein said timing-stabilization circuit comprises: an overflow-detection circuit which detects overflow when at least one of said plurality of variable-delay circuits has a delay exceeding the adjustable delay range, said overflow-detection circuit being connected to each of said independent delay-control circuits; a feedback loop for controlling delays of said plurality of variable-delay circuits; and a frequency divider which divides a frequency of said internal clock signal to generate frequency-divided clock signals used in said feedback loop, wherein said frequency divider lowers frequencies of said frequency-divided clock signals when said overflow-detection circuit detects.

Claim 6

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing stabilization circuit which generates a plurality of phase-adjusted clock signals by adjusting a timing of said internal clock signal by delaying said internal clock signal by a plurality of variable-delay circuits, each of at least two variable-delay circuits of said plurality of variable delay circuits being controlled separately by a corresponding one of independent delay-control circuits such that the phase-adjusted clock signals have phases independent of each other, wherein said timing-stabilization circuit comprises: an overflow-detection circuit which detects overflow when at least one of said plurality of variable-delay circuits has a delay exceeding the adjustable delay range, said overflow-detection circuit being connected to each of said independent delay-control circuits; a feedback loop for controlling delays of said plurality of variable-delay circuits; and a frequency divider which divides a frequency of said internal clock signal to generate frequency-divided clock signals used in said feedback loop, wherein said frequency divider lowers frequencies of said frequency-divided clock signals when said overflow-detection circuit detects.

Claim 7

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing stabilization circuit which generates a plurality of phase-adjusted clock signals by adjusting a timing of said internal clock signal by delaying said internal clock signal by a plurality of variable-delay circuits, each of at least two variable-delay circuits of said plurality of variable delay circuits being controlled separately by a corresponding one of independent delay-control circuits such that the phase-adjusted clock signals have phases independent of each other; an overflow-detection circuit which detects overflow when at least one of said plurality of variable-delay circuits has a delay exceeding the adjustable delay range, the said overflow-detection circuit being connected to each of said independent delay-control circuits, and a circuit which stops supply of said internal clock signal to said plurality of variable-delay circuits when said overflow-detection circuit detects overflow.

Claim 8

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing stabilization circuit which generates a plurality of phase-adjusted clock signals by adjusting a timing of said internal clock signal by delaying said internal clock signal by a plurality of variable-delay circuits, each of at least two variable-delay circuits of said plurality of variable delay circuits being controlled separately by a corresponding one of independent delay-control circuits such that the phase-adjusted clock signals have phases independent of each other; an overflow-detection circuit which detects overflow when at least one of said plurality of variable-delay circuits has a delay exceeding the adjustable delay range, the said overflow-detection circuit being connected to each of said independent delay-control circuits, and a circuit which stops supply of said internal clock signal to said plurality of variable-delay circuits when said overflow-detection circuit detects overflow.

Claim 9

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing stabilization circuit which generates a plurality of phase-adjusted clock signals by adjusting a timing of said internal clock signal by delaying said internal clock signal by a plurality of variable-delay circuits, each of at least two variable-delay circuits of said plurality of variable delay circuits being controlled separately by a corresponding one of independent delay-control circuits such that the phase-adjusted clock signals have phases independent of each other; and an overflow-detection circuit which detects overflow when at least one of said plurality of variable-delay circuits has a delay exceeding the adjustable delay range, the said overflow-detection circuit being connected to each of said independent delay-control circuits, and selection circuits which supply one of said internal clock signal and an inverse of said internal clock signal to internal circuits as substitutes for said phase-adjusted clock signals serving as synchronization signals in said internal circuits when said overflow-detection circuit detects overflow.

Claim 10

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing stabilization circuit which generates a plurality of phase-adjusted clock signals by adjusting a timing of said internal clock signal by delaying said internal clock signal by a plurality of variable-delay circuits, each of at least two variable-delay circuits of said plurality of variable delay circuits being controlled separately by a corresponding one of independent delay-control circuits such that the phase-adjusted clock signals have phases independent of each other; and an overflow-detection circuit which detects overflow when at least one of said plurality of variable-delay circuits has a delay exceeding the adjustable delay range, the said overflow-detection circuit being connected to each of said independent delay-control circuits, and selection circuits which supply one of said internal clock signal and an inverse of said internal clock signal to internal circuits as substitutes for said phase-adjusted clock signals serving as synchronization signals in said internal circuits when said overflow-detection circuit detects overflow.

Claim 11

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing stabilization circuit which generates a plurality of phase-adjusted clock signals by adjusting a timing of said internal clock signal by delaying said internal clock signal by a plurality of variable-delay circuits, each of at least two variable-delay circuits of said plurality of variable delay circuits being controlled separately by a corresponding one of independent delay-control circuits such that the phase-adjusted clock signals have phases independent of each other; an overflow-detection circuit which detects overflow when at least one of said plurality of variable-delay circuits has a delay exceeding the adjustable delay range, the said overflow-detection circuit being connected to each of said independent delay-control circuits, and selection circuits which supply one of said internal clock signal and an inverse of said internal clock signal to internal circuits as substitutes for said phase-adjusted clock signals serving as synchronization signals in said internal circuits when said overflow-detection circuit detects overflow, wherein said selection circuits supply said internal clock signal to said internal circuits in place of said phase-adjusted clock signals that are adjusted to have a phase displacement between 0° and 180° relative to said external clock signal, and supply said inverse of said internal clock signal to said internal circuits in place of said phase-adjusted clock signals that are adjusted to have a phase displacement between 180° and 360° relative to said external clock signal.

Claim 12

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing stabilization circuit which generates a plurality of phase-adjusted clock signals by adjusting a timing of said internal clock signal by delaying said internal clock signal by a plurality of variable-delay circuits, each of at least two variable-delay circuits of said plurality of variable delay circuits being controlled separately by a corresponding one of independent delay-control circuits such that the phase-adjusted clock signals have phases independent of each other; an overflow-detection circuit which detects overflow when at least one of said plurality of variable-delay circuits has a delay exceeding the adjustable delay range, the said overflow-detection circuit being connected to each of said independent delay-control circuits, and selection circuits which supply one of said internal clock signal and an inverse of said internal clock signal to internal circuits as substitutes for said phase-adjusted clock signals serving as synchronization signals in said internal circuits when said overflow-detection circuit detects overflow, wherein said selection circuits supply said internal clock signal to said internal circuits in place of said phase-adjusted clock signals that are adjusted to have a phase displacement between 0° and 180° relative to said external clock signal, and supply said inverse of said internal clock signal to said internal circuits in place of said phase-adjusted clock signals that are adjusted to have a phase displacement between 180° and 360° relative to said external clock signal.

Claim 13

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a timing of said internal clock signal by delaying said internal clock signal by a delay of a variable-delay circuit; an overflow-detection circuit which generates an overflow-detection signal when said delay of said variable-delay circuit is set to an upper end of an adjustable delay range; and an output circuit which is connected to said overflow-detection circuit, and outputs said overflow-detection signal to an exterior of said semiconductor device.

Claim 14

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a timing of said internal clock signal by delaying said internal clock signal by a delay of a variable-delay circuit; an overflow-detection circuit which generates an overflow-detection signal when said delay of said variable-delay circuit is set to an upper end of an adjustable delay range; and an output circuit which is connected to said overflow-detection circuit, and outputs said overflow-detection signal to an exterior of said semiconductor device.

Claim 15

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a delay of a variable-delay circuit as said variable-delay circuit delays said internal clock signal; and an overflow-detection circuit which detects overflow when said delay of said variable-delay circuit is set to an upper end of an adjustable delay range, wherein said timing-stabilization circuit comprises: a feedback loop for controlling said delay of said variable-delay circuit; and a frequency divider which divides a frequency of said internal clock signal to generate a frequency-divided clock signal used in said feedback loop, wherein said frequency divider lowers a frequency of said frequency-divided clock signal when said overflow-detection circuit detects overflow.

Claim 16

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a delay of a variable-delay circuit as said variable-delay circuit delays said internal clock signal; and an overflow-detection circuit which detects overflow when said delay of said variable-delay circuit is set to an upper end of an adjustable delay range, wherein said timing-stabilization circuit comprises: a feedback loop for controlling said delay of said variable-delay circuit; and a frequency divider which divides a frequency of said internal clock signal to generate a frequency-divided clock signal used in said feedback loop, wherein said frequency divider lowers a frequency of said frequency-divided clock signal when said overflow-detection circuit detects overflow.

Claim 17

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a delay of a variable-delay circuit as said variable-delay circuit delays said internal clock signal; an overflow-detection circuit which detects overflow when said delay of said variable-delay circuit is set to an upper end of an adjustable delay range; and a circuit which stops supply of said internal clock signal to said variable-delay circuit when said overflow-detection circuit detects overflow.

Claim 18

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a delay of a variable-delay circuit as said variable-delay circuit delays said internal clock signal; an overflow-detection circuit which detects overflow when said delay of said variable-delay circuit is set to an upper end of an adjustable delay range; and a circuit which stops supply of said internal clock signal to said variable-delay circuit when said overflow-detection circuit detects overflow.

Claim 19

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a delay of a rough-adjustment variable-delay circuit and a delay of a fine-adjustment variable-delay circuit as said rough-adjustment variable-delay circuit and said fine-adjustment variable-delay circuit delay said internal clock signal; and an overflow-detection circuit which detects overflow when said delay of said rough-adjustment variable-delay circuit is set to an upper end of an adjustable delay range.

Claim 20

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a delay of a rough-adjustment variable-delay circuit and a delay of a fine-adjustment variable-delay circuit as said rough-adjustment variable-delay circuit and said fine-adjustment variable-delay circuit delay said internal clock signal; and an overflow-detection circuit which detects overflow when said delay of said rough-adjustment variable-delay circuit is set to an upper end of an adjustable delay range.

Claim 21

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a delay of a variable-delay circuit as said variable-delay circuit delays said internal clock signal; an overflow-detection circuit which detects overflow when said delay of said variable-delay circuit is set to an upper end of an adjustable delay range; a selection circuit which supplies one of said internal clock signal and an inverse of said internal clock signal to an internal circuit as a substitute for said phase-adjusted clock signal serving as a synchronization signal in said internal circuit when said overflow-detection circuit detects overflow; and a control circuit which overrides operations of said selection circuit based on at least one externally provided signal such that said at least one externally provided signal determines which clock signal is selected by said selection circuit regardless of whether said overflow-detection circuit detects overflow.

Claim 22

A semiconductor device comprising: an input buffer buffering an external clock signal to supply an internal clock signal; a timing-stabilization circuit which generates a phase-adjusted clock signal by adjusting a delay of a variable-delay circuit as said variable-delay circuit delays said internal clock signal; an overflow-detection circuit which detects overflow when said delay of said variable-delay circuit is set to an upper end of an adjustable delay range; a selection circuit which supplies one of said internal clock signal and an inverse of said internal clock signal to an internal circuit as a substitute for said phase-adjusted clock signal serving as a synchronization signal in said internal circuit when said overflow-detection circuit detects overflow; and a control circuit which overrides operations of said selection circuit based on at least one externally provided signal such that said at least one externally provided signal determines which clock signal is selected by said selection circuit regardless of whether said overflow-detection circuit detects overflow.

Claim 23

A semiconductor device receiving an external clock signal, comprising: a variable-delay circuit receiving the external clock signal for producing a phase-adjusted clock signal to an internal circuit; a frequency divider receiving the clock signal to generate frequency divided clock signal to a phase comparator which controls a timing of the phase-adjusted clock signal; an overflow detection circuit detecting an overflow at the variable-delay circuit; and a gate circuit for controlling to supply the clock signal to the variable-delay circuit, wherein the gate circuit prevents to supply the clock signal and the frequency divider increases a dividing ratio, when the overflow-detection circuit detects the overflow.

Claim 24

A semiconductor device receiving an external clock signal, comprising: a variable-delay circuit receiving the external clock signal for producing a phase-adjusted clock signal to an internal circuit; a frequency divider receiving the clock signal to generate frequency divided clock signal to a phase comparator which controls a timing of the phase-adjusted clock signal; an overflow detection circuit detecting an overflow at the variable-delay circuit; and a gate circuit for controlling to supply the clock signal to the variable-delay circuit, wherein the gate circuit prevents to supply the clock signal and the frequency divider increases a dividing ratio, when the overflow-detection circuit detects the overflow.

Claim 25

A semiconductor device comprising: an input buffer buffering an external clock signal to output a first internal clock signal; a timing adjustment circuit delaying said first internal clock signal to generate a second internal clock signal and including a phase adjusting feedback loop by which a phase of said second internal clock signal is dynamically adjusted to have a predetermined relationship with said external clock signal; and an internal clock selection circuit receiving said first and second internal clock signals and selecting one of said first and second internal clock signals in response to an external input signal that is supplied from an exterior of the device to indicate a choice of one of said first and second internal clock signals, said internal clock selection circuit supplying an internal circuit with selected one of said first and second internal clock signals.

Claim 26

A semiconductor device comprising: an input buffer buffering an external clock signal to output a first internal clock signal; a timing adjustment circuit delaying said first internal clock signal to generate a second internal clock signal and including a phase adjusting feedback loop by which a phase of said second internal clock signal is dynamically adjusted to have a predetermined relationship with said external clock signal; and an internal clock selection circuit receiving said first and second internal clock signals and selecting one of said first and second internal clock signals in response to an external input signal that is supplied from an exterior of the device to indicate a choice of one of said first and second internal clock signals, said internal clock selection circuit supplying an internal circuit with selected one of said first and second internal clock signals.