Configuration and fabrication of semiconductor structure having n-channel channel-junction field-effect transistor

Claim 2

A structure comprising: an n-channel surface-channel insulated-gate field-effect transistor (“SCIGFET”) comprising a pair of laterally separated n-type source/drain zones situated in a semiconductor body along a major surface thereof, a p-type channel zone situated between the n-channel SCIGFET's source/drain zones in the semiconductor body along its major surface, a gate electrode situated over the channel zone of the n-channel SCIGFET and extending partially over its source/drain zones, and a gate dielectric layer separating the gate electrode of the n-channel SCIGFET from its source/drain and channel zones; and a normally off n-channel channel-junction insulated-gate field-effect transistor (“CJIGFET”) comprising a pair of laterally separated n-type source/drain zones situated in the semiconductor body along its major surface, an n-type channel zone extending between the n-channel CJIGFET's source/drain zones in the semiconductor body along its major surface and more lightly doped than the n-channel CJIGFET's source/drain zones, a gate electrode situated over the channel zone of the n-channel CJIGFET and extending partially over its source/drain zones, and a gate dielectric layer separating the gate electrode of the n-channel CJIGFET from its source/drain and channel zones, the gate dielectric layer of the n-channel CJIGFET being materially thicker than the gate dielectric layer of the n-channel SCIGFET.

Claim 3

A structure as in claim 1 wherein: the gate electrode of the n-channel SCIGFET comprises n-type semiconductor material; and the gate electrode of the n-channel CJIGFET comprises p-type semiconductor material.

Claim 4

A structure as in claim 1 wherein the n-channel CJIGFET is of greater channel length than the n-channel SCIGFET.

Claim 5

A structure as in claim 1 wherein the n-channel CJIGFET is of dimensions and dopant concentrations so as to conduct current through a field-induced surface channel that extends across the channel zone of the n-channel CJIGFET substantially up to its gate dielectric layer.

Claim 6

A structure as in claim 1 wherein the n-channel CJIGFET is of dimensions and dopant concentrations so as to conduct current through a metallurgical subsurface channel that extends across the channel zone of the n-channel CJIGFET below, and spaced apart from, its gate dielectric layer.

Claim 7

A structure as in claim 1 wherein the channel and source/drain zones of the n-channel CJIGFET contain arsenic as n-type dopant.

Claim 8

A structure as in claim 1 further including a p-channel SCIGFET comprising a pair of laterally separated p-type source/drain zones situated in the semiconductor body along its major surface, an n-type channel zone extending between the p-channel SCIGFET's source/drain zones in the semiconductor body along its major surface, a gate electrode situated over the channel zone of the p-channel SCIGFET and extending partially over its source/drain zones, and a gate dielectric layer separating the gate electrode of the p-channel SCIGFET from its source/drain and channel zones.

Claim 9

A structure as in claim 7 wherein: the gate electrode of the n-channel SCIGFET comprises n-type semiconductor material; and the gate electrodes of the p-channel SCIGFET and the n-channel CJIGFET comprise p-type semiconductor material.

Claim 10

A structure as in claim 8 wherein the semiconductor material of the gate electrodes comprises non-monocrystalline semiconductor material.

Claim 11

A structure as in claim 9 wherein the non-monocrystalline semiconductor material comprises polycrystalline semiconductor material.

Claim 12

A structure as in claim 7 wherein the gate dielectric layer of the n-channel CJIGFET is also materially thicker than the gate dielectric layer of the p-channel SCIGFET.

Claim 13

A structure as in claim 11 wherein the gate dielectric layers of the two SCIGFETs are of approximately equal thickness.

Claim 14

A structure as in claim 11 wherein the n-channel CJIGFET is of greater channel length than each SCIGFET.

Claim 15

A structure as in claim 11 wherein: the gate electrode of the n-channel SCIGFET comprises n-type semiconductor material; and the gate electrodes of the p-channel SCIGFET and the n-channel CJIGFET comprise p-type semiconductor material.

Claim 16

A structure as in claim 11 wherein the gate dielectric layer of the n-channel CJIGFET is at least twice as thick as the gate dielectric layer of each of the two SCIGFETs.

Claim 17

A structure as in claim 11 further including circuitry for providing voltages to the n-channel CJIGFET and the two SCIGFETs and for operating the n-channel CJIGFET across a materially greater voltage range than the two SCIGFETs.

Claim 18

A structure as in claim 16 wherein the voltage-providing/operating circuitry comprises: analog circuitry for providing voltages to the n-channel CJIGFET; and digital circuitry for providing voltages to the two SCIGFETs.

Claim 19

A structure as in claim 7 wherein the n-channel CJIGFET is of dimensions and dopant concentrations so as to conduct current through a field-induced surface channel that extends across the channel zone of the n-channel CJIGFET substantially up to its gate dielectric layer.

Claim 20

A structure as in claim 18 wherein the gate dielectric layer of the n-channel CJIGFET is also materially thicker than the gate dielectric layer of the p-channel SCIGFET.

Claim 21

A structure as in claim 19 wherein the gate dielectric layer of the n-channel CJIGFET is at least twice as thick as the gate dielectric layer of each of the two SCIGFETs.

Claim 22

A structure as in claim 19 further including circuitry for providing voltages to the n-channel CJIGFET and the two SCIGFETs and for operating the n-channel CJIGFET across a materially greater voltage range than the two SCIGFETs.

Claim 23

A structure as in claim 7 wherein the n-channel CJIGFET is of dimensions and dopant concentrations so as to conduct current through a metallurgical subsurface channel that extends across the channel zone of the n-channel CJIGFET below, and spaced apart from, its gate dielectric layer.

Claim 24

A structure as in claim 22 wherein the gate dielectric layer of the n-channel CJIGFET is also materially thicker than the gate dielectric layer of the p-channel SCIGFET.

Claim 25

A structure as in claim 23 wherein the gate dielectric layer of the n-channel CJIGFET is at least twice as thick as the gate dielectric layer of each of the two SCIGFETs.

Claim 26

A structure as in claim 23 further including circuitry for providing voltages to the n-channel CJIGFET and the two SCIGFETs and for operating the n-channel CJIGFET across a materially greater voltage range than the two SCIGFETs.

Claim 27

A structure as in claim 7 wherein the channel and source/drain zones of the n-channel CJIGFET contain arsenic as n-type dopant.

Claim 28

A structure as in claim 7 wherein the channel zone of each SCIGFET is part of body material having a net dopant concentration which reaches a primary local subsurface maximum below a channel surface depletion region that extends along the semiconductor body's major surface into that channel zone but no more than 0.4 μm below the semiconductor body's major surface.

Claim 29

A structure as in claim 27 wherein the net dopant concentration of the body material for each SCIGFET reaches a pair of additional vertically separated local subsurface maxima deeper below the semiconductor body's major surface than the primary local subsurface maximum in the net dopant concentration for that body material.

Claim 30

A structure as in claim 7 wherein the source/drain and channel zones of the n-channel CJIGFET form a composite pn junction with body material having a net dopant concentration which reaches a primary local subsurface maximum below the channel zone of the n-channel CJIGFET but no more than 0.6 μm below the semiconductor body's major surface.

Claim 31

A structure as in claim 29 wherein the net dopant concentration of the body material for the n-channel CJIGFET reaches a pair of additional vertically separated subsurface maxima deeper below the semiconductor body's major surface than the primary local subsurface maximum in the net dopant concentration for that body material.

Claim 32

A structure as in claim 7 wherein the channel zone of each SCIGFET has a net dopant concentration which reaches a local subsurface minimum along the semiconductor body's major surface at a location between that SCIGFET's source/drain zones.

Claim 33

A structure as in claim 31 wherein the channel zone of each SCIGFET is part of body material having a net dopant concentration which reaches a primary local subsurface maximum below a channel surface depletion region that extends along the semiconductor body's major surface into that channel zone but no more than 0.4 μm below the semiconductor body's major surface.

Claim 34

A structure as in claim 7 wherein the three gate dielectric layers comprise semiconductor material and oxygen.

Claim 35

A structure as in claim 33 wherein the gate dielectric layers of the two SCIGFETs further include nitrogen.

Claim 36

A structure as in claim 33 wherein the semiconductor body and the semiconductor material in the three gate dielectric layers both comprise silicon.

Claim 37

A structure as in claim 7 wherein each source/drain zone comprises a main source/drain portion and a more lightly doped source/drain extension laterally continuous with the main source/drain portion, the source/drain extensions of the two source/drain zones of each transistor terminating its channel zone along the semiconductor body's major surface.

Claim 38

A structure as in claim 7 further including a normally off p-channel further insulated-gate field-effect transistor (“IGFET”) comprising a pair of laterally separated p-type source/drain zones situated in the semiconductor body along its major surface, a channel zone extending between the p-channel further IGFET's source/drain zones in the semiconductor body along its major surface, a gate electrode situated over the channel zone of the p-channel further IGFET and extending partially over its source/drain zones, and a gate dielectric layer separating the gate electrode of the p-channel further IGFET from its source/drain and channel zones, the gate dielectric layers of the n-channel CJIGFET and the p-channel further IGFET both being materially thicker than the gate dielectric layers of the two SCIGFETs.

Claim 39

A structure as in claim 37 wherein: the gate dielectric layers of the two SCIGFETs are of approximately equal thickness; and the gate dielectric layers of the n-channel CJIGFET and the p-channel further IGFET are of approximately equal thickness.

Claim 40

A structure as in claim 37 wherein the n-channel CJIGFET and the p-channel further IGFET are each of greater channel length than each SCIGFET.

Claim 41

A structure as in claim 37 wherein the channel zone of the p-channel further IGFET is n-type such that the p-channel further IGFET is an SCIGFET.

Claim 42

A structure as in claim 40 wherein: the gate electrode of the n-channel SCIGFET comprises n-type semiconductor material; and the gate electrodes of the p-channel SCIGFET, the n-channel CJIGFET, and the p-channel further IGFET comprise p-type semiconductor material.

Claim 43

A structure as in claim 37 wherein the channel zone of the p-channel further IGFET is p-type and is more lightly doped than its source/drain zones such that the p-channel further IGFET is a CJIGFET.

Claim 44

A structure as in claim 42 wherein: the gate electrodes of the n-channel SCIGFET and the p-channel further IGFET comprise n-type semiconductor material; and the gate electrodes of the p-channel SCIGFET and the n-channel CJIGFET comprise p-type semiconductor material.

Claim 45

A structure as in claim 37 wherein the n-channel CJIGFET is of dimensions and dopant concentrations so as to conduct current through a field-induced surface channel that extends across the channel zone of the n-channel CJIGFET substantially up to its gate dielectric layer.

Claim 46

A structure as in claim 37 wherein the n-channel CJIGFET is of dimensions and dopant concentrations so as to conduct current through a metallurgical subsurface channel that extends across the channel zone of the n-channel CJIGFET below, and spaced apart from, its gate dielectric layer.

Claim 47

A structure as in claim 37 wherein the channel zone of each SCIGFET is part of body material having a net dopant concentration which reaches a primary local subsurface maximum below a channel surface depletion region that extends along the semiconductor body's major surface into that channel zone but no more than 0.4 μm below the semiconductor body's major surface.

Claim 48

A structure as in claim 37 wherein the source/drain and channel zones of the n-channel CJIGFET form a composite pn junction with body material having a net dopant concentration which reaches a primary local subsurface maximum below the channel zone of the n-channel CJIGFET but no more than 0.6 μm below the semiconductor body's major surface.

Claim 49

A structure as in claim 37 wherein the channel zone of each SCIGFET is part of body material having a net dopant concentration which reaches a primary local subsurface maximum below a channel surface depletion region that extends along the semiconductor body's major surface into that channel zone but no more than 0.4 μm below the semiconductor body's major surface.

Claim 50

A structure as in claim 37 wherein the gate dielectric layer of each of the n-channel CJIGFET and the p-channel further IGFET is at least twice as thick as the gate dielectric layer of each of the two SCIGFETs.

Claim 51

A structure as in claim 37 further including circuitry for providing voltages to the n-channel CJIGFET, the two SCIGFETs, and the p-channel further IGFET and for operating the n-channel CJIGFET and the p-channel further IGFET across a materially greater voltage range than the two SCIGFETs.

Claim 52

A structure as in claim 50 wherein the voltage-providing/operating circuitry comprises: analog circuitry for providing voltages to the n-channel CJIGFET and the p-channel further IGFET; and digital circuitry for providing voltages to the two SCIGFETs.

Claim 53

A structure as in claim 1 wherein the gate dielectric layer of the n-channel CJIGFET is at least twice as thick as the gate dielectric layer of the n-channel SCIGFET.

Claim 54

A structure as in claim 1 further including circuitry for providing voltages to the n-channel CJIGFET and the n-channel SCIGFET and for operating the n-channel CJIGFET across a materially greater voltage range than the n-channel SCIGFET.

Claim 55

A structure as in claim 53 wherein the voltage-providing/operating circuitry comprises: analog circuitry for providing voltages to the n-channel CJIGFET; and digital circuitry for providing voltages to the n-channel SCIGFET.

Claim 56

A structure comprising: an n-channel surface-channel insulated-gate field-effect transistor (“SCIGFET”) comprising a pair of laterally separated n-type source/drain zones situated in a semiconductor body along a major surface thereof, a p-type channel zone situated between the n-channel SCIGFET's source/drain zones in the semiconductor body along its major surface, a gate electrode situated over the channel zone of the n-channel SCIGFET and extending partially over its source/drain zones, and a gate dielectric layer separating the gate electrode of the n-channel SCIGFET from its source/drain and channel zones; and a normally off n-channel channel-junction insulated-gate field-effect transistor (“CJIGFET”) comprising a pair of laterally separated n-type source/drain zones situated in the semiconductor body along its major surface, an n-type channel zone extending between the n-channel CJIGFET's source/drain zones in the semiconductor body along its major surface and more lightly doped than the n-channel CJIGFET's source/drain zones, a gate electrode situated over the channel zone of the n-channel CJIGFET and extending partially over its source/drain zones, and a gate dielectric layer separating the gate electrode of the n-channel CJIGFET from its source/drain and channel zones, the n-channel CJIGFET being of dimensions and dopant concentrations so as to conduct current through a field-induced surface channel that extends across the channel zone of the n-channel CJIGFET substantially up to its gate dielectric layer.

Claim 57

A structure comprising: an n-channel surface-channel insulated-gate field-effect transistor (“SCIGFET”) comprising a pair of laterally separated n-type source/drain zones situated in a semiconductor body along a major surface thereof, a p-type channel zone situated between the n-channel SCIGFET's source/drain zones in the semiconductor body along its major surface, a gate electrode situated over the channel zone of the n-channel SCIGFET and extending partially over its source/drain zones, and a gate dielectric layer separating the gate electrode of the n-channel SCIGFET from its source/drain and channel zones; and a normally off n-channel channel-junction insulated-gate field-effect transistor (“CJIGFET”) comprising a pair of laterally separated n-type source/drain zones situated in the semiconductor body along its major surface, an n-type channel zone extending between the n-channel CJIGFET's source/drain zones in the semiconductor body along its major surface and more lightly doped than the n-channel CJIGFET's source/drain zones, a gate electrode situated over the channel zone of the n-channel CJIGFET and extending partially over its source/drain zones, and a gate dielectric layer separating the gate electrode of the n-channel CJIGFET from its source/drain and channel zones, the n-channel CJIGFET being of dimensions and dopant concentrations so as to conduct current through a field-induced surface channel that extends across the channel zone of the n-channel CJIGFET substantially up to its gate dielectric layer.

Claim 58

A structure as in claim 55 wherein the n-channel CJIGFET is of greater channel length than the n-channel SCIGFET.

Claim 59

A structure as in claim 55 further including circuitry for providing voltages to the n-channel CJIGFET and the n-channel SCIGFET and for operating the n-channel CJIGFET across a materially greater voltage range than the n-channel SCIGFET.

Claim 60

A structure as in claim 57 wherein the voltage-providing/operating circuitry comprises: analog circuitry for providing voltages to the n-channel CJIGFET; and digital circuitry for providing voltages to the n-channel SCIGFET.

Claim 61

A structure as in claim 55 further including a p-channel SCIGFET comprising a pair of laterally separated p-type source/drain zones situated in the semiconductor body along its major surface, an n-type channel zone extending between the p-channel SCIGFET's source/drain zones in the semiconductor body along its major surface, a gate electrode situated over the channel zone of the p-channel SCIGFET and extending partially over its source/drain zones, and a gate dielectric layer separating the gate electrode of the p-channel SCIGFET from its source/drain and channel zones.

Claim 62

A structure as in claim 59 wherein the n-channel CJIGFET is of greater channel length than each SCIGFET.

Claim 63

A structure as in claim 59 further including circuitry for providing voltages to the n-channel CJIGFET and the two SCIGFETs and for operating the n-channel CJIGFET across a materially greater voltage range than the two SCIGFETs.

Claim 64

A structure as in claim 61 wherein the voltage-providing/operating circuitry comprises: analog circuitry for providing voltages to the n-channel CJIGFET; and digital circuitry for providing voltages to the two SCIGFETs.

Claim 65

A structure as in claim 59 further including a normally off p-channel further insulated-gate field-effect transistor (“IGFET”) comprising a pair of laterally separated p-type source/drain zones situated in the semiconductor body along its major surface, a channel zone extending between the p-channel further IGFET's source/drain zones in the semiconductor body along its major surface, a gate electrode situated over the channel zone of the p-channel further IGFET and extending partially over its source/drain zones, and a gate dielectric layer separating the gate electrode of the p-channel further IGFET from its source/drain and channel zones.

Claim 66

A structure as in claim 63 wherein the n-channel CJIGFET and the p-channel further IGFET are each of greater channel length than each SCIGFET.

Claim 67

A structure as in claim 63 further including circuitry for providing voltages to the n-channel CJIGFET, the two SCIGFETs, and the p-channel further IGFET and for operating the n-channel CJIGFET and the p-channel further IGFET across a materially greater voltage range than the two SCIGFETs.

Claim 68

A structure as in claim 65 wherein the voltage-providing/operating circuitry comprises: analog circuitry for providing voltages to the n-channel CJIGFET and the p-channel further IGFET; and digital circuitry for providing voltages to the two SCIGFETs.