US5942780A
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Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate
Assignee: Lattice Semiconductor Corp
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Filing: 1996-08-09
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Granted: 1999-08-24
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Expires: 2016-08-09
Abstract
Abstract An integrated circuit ("IC") having three different oxide layer thicknesses and a process for manufacturing the IC using a single oxide growth step is provided. A first region is formed on a substrate surface with oxidation enhancing properties. A second region is formed on the substrate surface with a dose of nitrogen that retards oxidation. An oxide layer is grown from the first and the second regions and a third region of the substrate such that the first, second, and third regions yield a first oxide layer for the capacitor, a second oxide layer for the read transistor and a third oxide layer for the write transistor.
Inventors
- 👤 Radu M. Barsan
- 👤 Xiao-Yu Li
- 👤 Sunil Mehta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:24
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B41/60; H10B69/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
83 words
An integrated circuit comprising: (a) a substrate; (b) an oxide layer where the oxide layer includes a first oxide thickness, a second oxide thickness different from the first by (Δ 1 ) and a third oxide thickness different from the second by (Δ 2 ), wherein the first oxide thickness is an approximately 150 Å gate oxide layer, the second oxide thickness is an approximately 80 Å gate oxide layer and, the third oxide thicknesses is an approximately 90 Å tunnel oxide layer.
Claim 2
Dependent Claim
83 words
An integrated circuit comprising: (a) a substrate; (b) an oxide layer where the oxide layer includes a first oxide thickness, a second oxide thickness different from the first by (Δ 1 ) and a third oxide thickness different from the second by (Δ 2 ), wherein the first oxide thickness is an approximately 150 Å gate oxide layer, the second oxide thickness is an approximately 80 Å gate oxide layer and, the third oxide thicknesses is an approximately 90 Å tunnel oxide layer.
Claim 3
Dependent Claim
83 words
An integrated circuit comprising: (a) a substrate; (b) an oxide layer where the oxide layer includes a first oxide thickness, a second oxide thickness different from the first by (Δ 1 ) and a third oxide thickness different from the second by (Δ 2 ), wherein the first oxide thickness is an approximately 150 Å gate oxide layer, the second oxide thickness is an approximately 70 Å gate oxide layer and, the third oxide thickness is an approximately 90 Å tunnel oxide layer.
Claim 4
Dependent Claim
83 words
An integrated circuit comprising: (a) a substrate; (b) an oxide layer where the oxide layer includes a first oxide thickness, a second oxide thickness different from the first by (Δ 1 ) and a third oxide thickness different from the second by (Δ 2 ), wherein the first oxide thickness is an approximately 150 Å gate oxide layer, the second oxide thickness is an approximately 70 Å gate oxide layer and, the third oxide thickness is an approximately 90 Å tunnel oxide layer.
Claim 5
Dependent Claim
83 words
An integrated circuit comprising: (a) a substrate; (b) an oxide layer where the oxide layer includes a first oxide thickness, a second oxide thickness different from the first by (Δ 1 ) and a third oxide thickness different from the second by (Δ 2 ), wherein the first oxide thickness is an approximately 150 Å gate oxide layer, the second oxide thickness is an approximately 50 Å gate oxide layer and, the third oxide thickness is an approximately 90 Å tunnel oxide layer.
Claim 6
Dependent Claim
83 words
An integrated circuit comprising: (a) a substrate; (b) an oxide layer where the oxide layer includes a first oxide thickness, a second oxide thickness different from the first by (Δ 1 ) and a third oxide thickness different from the second by (Δ 2 ), wherein the first oxide thickness is an approximately 150 Å gate oxide layer, the second oxide thickness is an approximately 50 Å gate oxide layer and, the third oxide thickness is an approximately 90 Å tunnel oxide layer.
Claim 7
Dependent Claim
123 words
A non-volatile memory cell on a silicon wafer substrate, comprising: (a) a first transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a first oxide thickness; (b) a second transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a second oxide thickness; and, (c) a tunnel capacitor having a tunnel oxide layer having a third oxide thickness, wherein the first oxide thickness is an approximately 150 Å gate oxide layer, the second oxide thickness is an approximately 80 Å gate oxide layer and, the third oxide thickness is an approximately 90 Å tunnel oxide layer.
Claim 8
Dependent Claim
123 words
A non-volatile memory cell on a silicon wafer substrate, comprising: (a) a first transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a first oxide thickness; (b) a second transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a second oxide thickness; and, (c) a tunnel capacitor having a tunnel oxide layer having a third oxide thickness, wherein the first oxide thickness is an approximately 150 Å gate oxide layer, the second oxide thickness is an approximately 80 Å gate oxide layer and, the third oxide thickness is an approximately 90 Å tunnel oxide layer.
Claim 9
Dependent Claim
123 words
A non-volatile memory cell on a silicon wafer substrate, comprising: (a) a first transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a first oxide thickness; (b) a second transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a second oxide thickness; and, (c) a tunnel capacitor having a tunnel oxide layer having a third oxide thickness, wherein the first oxide thickness is an approximately 150 Å gate oxide layer, the second oxide thickness is an approximately 70 Å gate oxide layer and, the third oxide thickness is an approximately 90 Å tunnel oxide layer.
Claim 10
Dependent Claim
123 words
A non-volatile memory cell on a silicon wafer substrate, comprising: (a) a first transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a first oxide thickness; (b) a second transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a second oxide thickness; and, (c) a tunnel capacitor having a tunnel oxide layer having a third oxide thickness, wherein the first oxide thickness is an approximately 150 Å gate oxide layer, the second oxide thickness is an approximately 70 Å gate oxide layer and, the third oxide thickness is an approximately 90 Å tunnel oxide layer.
Claim 11
Dependent Claim
123 words
A non-volatile memory cell on a silicon wafer substrate, comprising: (a) a first transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a first oxide thickness; b) a second transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a second oxide thickness; and, (c) a tunnel capacitor having a tunnel oxide layer having a third oxide thickness, wherein the first oxide thickness is an approximately 150 Å gate oxide layer, the second oxide thickness is an approximately 50 Å gate oxide layer and, the third oxide thickness is an approximately 90 Å tunnel oxide layer.
Claim 12
Dependent Claim
123 words
A non-volatile memory cell on a silicon wafer substrate, comprising: (a) a first transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a first oxide thickness; b) a second transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a second oxide thickness; and, (c) a tunnel capacitor having a tunnel oxide layer having a third oxide thickness, wherein the first oxide thickness is an approximately 150 Å gate oxide layer, the second oxide thickness is an approximately 50 Å gate oxide layer and, the third oxide thickness is an approximately 90 Å tunnel oxide layer.
References Cited (Backward Citations)
US4651406A
Cited
US4716126A
Cited
US4807003A
Cited
US4924278A
Cited
US5532181A
Cited
US5330920A
Cited
US5308787A
Cited
US5633520A
Cited
US5432114A
Cited
US5587945A
Cited
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