Semiconductor device including a memory cell and peripheral portion and method for forming same

Claim 1

A semiconductor device comprising: a substrate having a primary surface; a memory cell provided on the substrate, the memory cell including a P-channel transistor, the P-channel transistor having an N-type gate, wherein the P-channel transistor of the memory cell has a device region in the primary surface of the substrate, the device region including a surface channel region having a dopant concentration of less than 1E16 atoms per cubic cm at a depth no more than approximately 0.1 microns from the primary surface of the substrate, a punchthrough region having a maximum dopant concentration of 1E17 to 1E18 atoms per cubic cm at a depth within a range of 0.1 to 0.3 microns from the primary surface of the substrate, and a background region having a maximum dopant concentration of approximately 1E16 to 1E17 at a depth within a range of approximately 0.2 to 0.5 microns from the primary surface of the substrate; and a peripheral portion provided on the substrate, the peripheral portion including a P-channel transistor, the P-channel transistor having a P-type gate.

Claim 9

A method of forming a semiconductor device comprising the steps of: providing a substrate having a primary surface; forming a memory cell provided on the substrate, the memory cell including a P-channel transistor, the P-channel transistor having a N-type gate, wherein: the P-channel transistor of the memory cell includes a device region in the primary surface of the substrate, the device region of P-channel transistor of the memory cell having a surface channel region and a punchthrough region; the surface channel region of the P-channel transistor of the memory cell is formed by implanting boron at a dose of approximately 1E12 to 1E13 ions per cm 2 at an energy of approximately 5 to 50 KeV; and the punchthrough region of the P-channel transistor of the memory cell is formed by implanting arsenic or antimony at a dose of approximately 1E12 to 1E13 ions per cm 2 at an energy of approximately 50 to 300 KeV; and forming a peripheral portion provided on the substrate, the peripheral portion including a P-channel transistor, the P-channel transistor having a P-type gate, wherein: the P-channel transistor of the peripheral portion includes a device region in the primary surface of the substrate, the device region of the P-channel transistor of the peripheral portion having a surface channel region; and the surface channel region of the P-channel transistor of the peripheral portion is formed by implanting phosphorous at a dose of approximately 1E12 to 1E13 ions per cm 2 at an energy of approximately 5 to 50 KeV.

Claim 10

A method of forming a semiconductor device comprising the steps of: providing a substrate having a primary surface; forming a memory cell provided on the substrate, the memory cell including a P-channel transistor, the P-channel transistor having a N-type gate, wherein: the P-channel transistor of the memory cell includes a device region in the primary surface of the substrate, the device region of P-channel transistor of the memory cell having a surface channel region and a punchthrough region; the surface channel region of the P-channel transistor of the memory cell is formed by implanting boron at a dose of approximately 1E12 to 1E13 ions per cm 2 at an energy of approximately 5 to 50 KeV; and the punchthrough region of the P-channel transistor of the memory cell is formed by implanting arsenic or antimony at a dose of approximately 1E12 to 1E13 ions per cm 2 at an energy of approximately 50 to 300 KeV; and forming a peripheral portion provided on the substrate, the peripheral portion including a P-channel transistor, the P-channel transistor having a P-type gate, wherein: the P-channel transistor of the peripheral portion includes a device region in the primary surface of the substrate, the device region of the P-channel transistor of the peripheral portion having a surface channel region; and the surface channel region of the P-channel transistor of the peripheral portion is formed by implanting phosphorous at a dose of approximately 1E12 to 1E13 ions per cm 2 at an energy of approximately 5 to 50 KeV.