US5952701A
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Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value
Assignee: National Semiconductor Corp
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Filing: 1997-08-18
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Granted: 1999-09-14
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Expires: 2017-08-18
Abstract
Abstract A pair of complementary CJIGFETs (100 and 160) are created from a body of semiconductor material (102 and 104). Each CJIGFET is formed with (a) a pair of laterally separated source/drain zones (112 and 114 or 172 and 174) situated along the upper surface of the semiconductor body, (b) a channel region (110 or 170) extending between the source/drain zones, and (c) a gate electrode (118 or 178) overlying, and electrically insulated from, the channel region. The gate electrode of each CJIGFET has a Fermi energy level within 0.3 ev of the middle of the energy band gap of the semiconductor material. One of the transistors typically conducts current according to a field-induced-channel mode while the other transistor conducts current according to a metallurgical-channel mode. The magnitude of the threshold voltage for each CJIGFET is normally no more than 0.5 V.
Inventors
- 👤 Constantin Bulucea
- 👤 Daniel C. Kerr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:41
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/0172; H10D84/8311
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
143 words
A complementary-transistor structure comprising: a body of semiconductor material having an upper semiconductor surface, the semiconductor material characterized by an electron affinity χ S and a valence-to-conduction band-gap energy E G ; and complementary first and second field-effect transistors, each comprising: a pair of laterally separated source/drain zones situated in the semiconductor body along the upper semiconductor surface; a channel region extending between the source/drain zones in the semiconductor body along the upper semiconductor surface; and a gate electrode overlying the channel region, electrically insulated from the channel region, and having a work function within 0.3 eV of χ S +E G /2; where the source/drain zones and channel region of the first transistor are of a first conductivity type, and the source/drain zones and channel region of the second transistor are of a second conductivity type opposite to the first conductivity type.
Claim 2
Dependent Claim
143 words
A complementary-transistor structure comprising: a body of semiconductor material having an upper semiconductor surface, the semiconductor material characterized by an electron affinity χ S and a valence-to-conduction band-gap energy E G ; and complementary first and second field-effect transistors, each comprising: a pair of laterally separated source/drain zones situated in the semiconductor body along the upper semiconductor surface; a channel region extending between the source/drain zones in the semiconductor body along the upper semiconductor surface; and a gate electrode overlying the channel region, electrically insulated from the channel region, and having a work function within 0.3 eV of χ S +E G /2; where the source/drain zones and channel region of the first transistor are of a first conductivity type, and the source/drain zones and channel region of the second transistor are of a second conductivity type opposite to the first conductivity type.
Claim 3
Dependent Claim
29 words
A structure as in claim 1 wherein: one of the transistors conducts current according to a field-induced-channel mode; and the other transistor conducts current according to a metallurgical-channel mode.
Claim 4
Dependent Claim
23 words
A structure as in claim 1 wherein the gate electrodes of both transistors consist of electrically conductive material of largely the same type.
Claim 5
Dependent Claim
81 words
A structure as in claim 3 wherein: the work functions of the gate electrodes are largely equal; the first and second conductivity types respectively are n-type and p-type whereby the first and second transistors respectively are n-channel and p-channel transistors; and the first and second transistors are respectively operable in field-induced-channel and metallurgical-channel modes when the work functions are greater than χ S +E G /2, and vice versa when the work functions are less than χ S +E G /2.
Claim 6
Dependent Claim
27 words
A structure as in claim 1 wherein the work function of the gate electrode of each transistor is within 0.2 eV of χ S +E G /2.
Claim 7
Dependent Claim
27 words
A structure as in claim 1 wherein the work function of the gate electrode of each transistor is within 0.15 eV of χ S +E G /2.
Claim 8
Dependent Claim
14 words
A structure as in claim 1 wherein each transistor is a normally off device.
Claim 9
Dependent Claim
21 words
A structure as in claim 1 where each transistor has a threshold voltage whose magnitude is no more than 0.5 V.
Claim 10
Dependent Claim
92 words
A structure as in claim 1 wherein each transistor has a threshold voltage whose magnitude is within 0.3 V of value V TX determined from: ##EQU51## where k is Boltzmann's constant, T is the absolute temperature, q is the electronic charge, N CX is the average net dopant concentration of the channel region for that transistor at the surface-channel-to-buried-channel crossover location, and n i is the intrinsic carrier concentration of the semiconductor material, the threshold voltage of one of the transistors being positive, the threshold voltage of the other transistor being negative.
Claim 11
Dependent Claim
27 words
A structure as in claim 1 wherein the source/drain zones of each transistor extend deeper below the upper semiconductor surface than the channel region of that transistor.
Claim 12
Dependent Claim
47 words
A structure as in claim 1 wherein the semiconductor body further includes, for each transistor, a body region that adjoins, and is of opposite conductivity type to, the channel region of that transistor, the body region and channel region of each transistor thereby forming a pn junction.
Claim 13
Dependent Claim
39 words
A structure as in claim 11 wherein the channel region of each transistor is substantially depleted of charge when the gate electrode, body region, and one of the source/drain zones of that transistor are at substantially the same voltage.
Claim 14
Dependent Claim
176 words
A structure as in claim 11 wherein the channel region of each transistor has an average net dopant concentration that differs from value N CX determined from: ##EQU52## where y JMIN is the depth below the upper semiconductor surface of that channel region at the surface-channel-to-buried-channel-crossover location, N CX is the average net dopant concentration of that channel region at the surface-channel-to-buried-channel crossover location, N B is the average net dopant concentration of the body region for that transistor, n i is the intrinsic carrier concentration of the semiconductor material, and L D (C) is the average extrinsic Debye length given from: ##EQU53## where k is Boltzmann's constant, T is the absolute temperature, q is the electronic charge, and .di-elect cons. S is the permittivity of the semiconductor material, the average net dopant concentration in the channel region of one of the transistors being greater than N CX for that one transistor, the average net dopant concentration in the channel region of the other of the transistors being less than N CX for that other transistor.
Claim 15
Dependent Claim
85 words
A structure as in claim 13 wherein charge carriers that move between the source/drain zones of each transistor when it is turned on flow through that transistor's channel region (a) along a buried channel situated below the upper semiconductor surface when the average net dopant concentration in that transistor's channel region is greater than N CX and (b) along a surface channel situated along the upper semiconductor surface when the average net dopant concentration in that transistor's channel region is less than N CX .
Claim 16
Dependent Claim
28 words
A structure as in claim 14 wherein (a) the buried channel consists of largely undepleted semiconductor material and (b) the surface channel is created largely by field-induced inversion.
Claim 17
Dependent Claim
74 words
A structure as in claim 13 wherein: a specified one of the transistors conducts current according to a field-induced-channel mode, the average net dopant concentration in the specified transistor's channel region being less than N CX for the specified transistor; and the remaining one of the transistors conducts current according to a metallurgical-channel mode, the average net dopant concentration in the remaining transistor's channel region being greater than N CX for the remaining transistor.
Claim 18
Dependent Claim
56 words
A structure as in claim 16 wherein: the work functions of the gate electrodes are largely equal; the specified transistor is an n-channel transistor when the work functions are greater than χ S +E G /2; and the specified transistor is a p-channel transistor when the work functions are less than χ S +E G /2.
Claim 19
Dependent Claim
29 words
A structure as in claim 1 wherein the semiconductor material consists primarily of silicon, and each gate electrode consists primarily of at least one of molybdenum, tungsten, and cobalt.
Claim 20
Dependent Claim
25 words
A structure as in claim 1 wherein the semiconductor material consists primarily of silicon, and each gate electrode consists primarily of conductively doped polycrystalline silicon-germanium.
Claim 21
Dependent Claim
13 words
A structure as in claim 19 wherein the polycrystalline silicon-germanium is p doped.
Claim 22
Independent Claim
273 words
A method of fabricating a complementary-transistor structure from a body of semiconductor material having an upper semiconductor surface, the semiconductor body comprising a p-type body region and an n-type body region that extend to the upper semiconductor surface, the semiconductor material characterized by an electron affinity χ S and a valence-to-conduction bandgap energy E G , the method comprising the steps of: introducing first n-type and p-type dopants respectively into the p-type and n-type body regions to respectively define an n-type channel region and a p-type channel region that extend to the upper semiconductor surface; providing a first gate dielectric layer and a second gate dielectric layer respectively over the n-type and p-type channel regions; forming a first gate electrode and a second gate electrode respectively over the first and second gate dielectric layers respectively above the n-type and p-type channel regions such that each gate electrode has a work function within 0.3 eV of χ S +E G /2; selectively introducing second n-type and p-type dopants respectively into the p-type and n-type body regions to respectively form (a) a pair of laterally separated n-type source/drain zones which extend to the upper semiconductor surface and between which the n-type channel region extends and (b) a pair of laterally separated p-type source/drain zones which extend to the upper semiconductor surface and between which the p-type channel region extends, an n-channel field-effect transistor comprising the n-type source/drain zones, the n-type channel region, the first gate dielectric layer, and the first gate electrode, a p-channel field-effect transistor comprising the p-type source/drain zones, the p-type channel region, the second gate dielectric layer, and the second gate electrode.
Claim 23
Independent Claim
273 words
A method of fabricating a complementary-transistor structure from a body of semiconductor material having an upper semiconductor surface, the semiconductor body comprising a p-type body region and an n-type body region that extend to the upper semiconductor surface, the semiconductor material characterized by an electron affinity χ S and a valence-to-conduction bandgap energy E G , the method comprising the steps of: introducing first n-type and p-type dopants respectively into the p-type and n-type body regions to respectively define an n-type channel region and a p-type channel region that extend to the upper semiconductor surface; providing a first gate dielectric layer and a second gate dielectric layer respectively over the n-type and p-type channel regions; forming a first gate electrode and a second gate electrode respectively over the first and second gate dielectric layers respectively above the n-type and p-type channel regions such that each gate electrode has a work function within 0.3 eV of χ S +E G /2; selectively introducing second n-type and p-type dopants respectively into the p-type and n-type body regions to respectively form (a) a pair of laterally separated n-type source/drain zones which extend to the upper semiconductor surface and between which the n-type channel region extends and (b) a pair of laterally separated p-type source/drain zones which extend to the upper semiconductor surface and between which the p-type channel region extends, an n-channel field-effect transistor comprising the n-type source/drain zones, the n-type channel region, the first gate dielectric layer, and the first gate electrode, a p-channel field-effect transistor comprising the p-type source/drain zones, the p-type channel region, the second gate dielectric layer, and the second gate electrode.
Claim 24
Dependent Claim
22 words
A method as in claim 21 wherein the forming step entails forming both gate electrodes from largely the same electrically conductive material.
Claim 25
Dependent Claim
106 words
A method as in claim 22 wherein the first dopants are introduced into the body regions under such doping conditions that each transistor attains a threshold voltage whose magnitude is within 0.3 V of value V TX determined from: ##EQU54## where k is Boltzmann's constant, T is the absolute temperature, q is the electronic charge, N CX is the average net dopant concentration of the channel region for that transistor at the surface-channel-to-buried-channel crossover location, and n i is the intrinsic carrier concentration of the semiconductor material, the threshold voltage of one of the transistors being positive, the threshold voltage of the other transistor being negative.
Claim 26
Dependent Claim
150 words
A method as in claim 22 wherein the channel region of each transistor has an average net dopant concentration differs from value N CX determined from: ##EQU55## where y JMIN is the depth below the upper semiconductor surface of that channel region at the surface-channel-to-buried-channel-crossover location, N CX is the average net dopant concentration of that channel region at the surface-channel-to-buried-channel crossover location, L.sub.(DC) is the average extrinsic Debye length at dopant concentration N CX , N B is the average net dopant concentration of the body region for that transistor, and n i is the intrinsic carrier concentration of the semiconductor material, the average net dopant concentration in the channel region of one of the transistors being greater than N CX for that one transistor, the average net dopant concentration in the channel region of the other of the transistors being less than N CX for that other transistor.
Claim 27
Dependent Claim
29 words
A method as in claim 22 wherein the forming step entails forming the gate electrodes primarily from at least one of molybdenum, tungsten, cobalt, and conductively doped polycrystalline silicon-germanium.
References Cited (Backward Citations)
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