Patent US6576147B2 successfully refreshed from Google Patents.
Patent US7120882B2 successfully refreshed from Google Patents.
US7120882B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of setting process parameter and method of setting process parameter and/or design rule
Assignee: Kioxia Corp
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Filing: 2005-04-14
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Granted: 2006-10-10
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Expires: 2025-04-14
Abstract
Abstract Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.
Inventors
- 👤 Toshiya Kotani
- 👤 Satoshi Tanaka
- 👤 Koji Hashimoto
- 👤 Soichi Inoue
- 👤 Ichiro Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:20
CPC Classifications
H; H10; H10P; H10P76/00; H10P74/00; H10P74/23
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
189 words
A method of setting at least one of a process parameter and a design rule for use in manufacturing a semiconductor integrated circuit, comprising: compacting a first pattern by using design rule information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit; obtaining chip size information of the semiconductor integrated circuit, which relates to the second pattern; obtaining a third pattern by using process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer; comparing the third pattern with the second pattern to obtain a comparison result; extracting a dangerous spot from the second pattern by using the comparison result to obtain dangerous spot information, the dangerous spot not having prescribed latitude; determining whether the chip size information and the dangerous spot information satisfy evaluation conditions, respectively; and changing at least one of the design rule information and the process parameter information when at least one of the chip size information and the dangerous spot information is determined not to satisfy the evaluation conditions.
Claim 2
Independent Claim
189 words
A method of setting at least one of a process parameter and a design rule for use in manufacturing a semiconductor integrated circuit, comprising: compacting a first pattern by using design rule information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit; obtaining chip size information of the semiconductor integrated circuit, which relates to the second pattern; obtaining a third pattern by using process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer; comparing the third pattern with the second pattern to obtain a comparison result; extracting a dangerous spot from the second pattern by using the comparison result to obtain dangerous spot information, the dangerous spot not having prescribed latitude; determining whether the chip size information and the dangerous spot information satisfy evaluation conditions, respectively; and changing at least one of the design rule information and the process parameter information when at least one of the chip size information and the dangerous spot information is determined not to satisfy the evaluation conditions.
Claim 3
Dependent Claim
42 words
The method according to claim 1 , further comprising: setting the changed design rule information as the design rule information in compacting the first pattern; and setting the changed process parameter information as the process parameter information in obtaining the third pattern.
Claim 4
Dependent Claim
56 words
The method according to claim 2 , wherein said changing at least one of the design rule information and the process parameter information to said determining whether the chip size information and the dangerous spot information satisfy evaluation conditions are repeated until the chip size information and the dangerous spot information satisfy the evaluation conditions, respectively.
Claim 5
Dependent Claim
15 words
The method according to claim 1 , wherein the third pattern is predicted by simulation.
Claim 6
Dependent Claim
31 words
The method according to claim 1 , wherein the third pattern is predicted by using photolithography mask data or electron-beam lithography data obtained by performing proximity correction on the second pattern.
Claim 7
Dependent Claim
40 words
The method according to claim 1 , wherein the third pattern corresponds to a shape of a resist pattern on the semiconductor wafer or a shape of a pattern of the semiconductor wafer processed, said shapes having been experimentally obtained.
Claim 8
Dependent Claim
47 words
The method according to claim 1 , wherein the dangerous spot information is obtained by changing at least one of an exposure dose, an exposure focus, an average size of a mask pattern, a size variation of a mask pattern, a lens aberration, and an overlay error.
Claim 9
Dependent Claim
55 words
The method according to claim 1 , wherein the process parameter information includes at least one of wavelength of exposure light, numerical aperture (NA) of a lens of an exposure apparatus, an illumination shape (σ, ε) of an exposure apparatus, phase of a photomask, transmittance of a photomask, developing process parameter, and resist process parameter.
Claim 10
Dependent Claim
24 words
A method of manufacturing a semiconductor device, comprising forming a pattern on a semiconductor substrate by using the method according to claim 1 .
Claim 11
Independent Claim
203 words
A system for setting at least one of a process parameter and a design rule for use in manufacturing a semiconductor integrated circuit, comprising: means for compacting a first pattern by using design rule information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit; means for obtaining chip size information of the semiconductor integrated circuit, which relates to the second pattern; means for obtaining a third pattern by using process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer; means for comparing the third pattern with the second pattern to obtain a comparison result; means for extracting a dangerous spot from the second pattern by using the comparison result to obtain dangerous spot information, the dangerous spot not having prescribed latitude; means for determining whether the chip size information and the dangerous spot information satisfy evaluation conditions, respectively; and means for changing at least one of the design rule information and the process parameter information when at least one of the chip size information and the dangerous spot information is determined not to satisfy the evaluation conditions.
Claim 12
Independent Claim
203 words
A system for setting at least one of a process parameter and a design rule for use in manufacturing a semiconductor integrated circuit, comprising: means for compacting a first pattern by using design rule information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit; means for obtaining chip size information of the semiconductor integrated circuit, which relates to the second pattern; means for obtaining a third pattern by using process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer; means for comparing the third pattern with the second pattern to obtain a comparison result; means for extracting a dangerous spot from the second pattern by using the comparison result to obtain dangerous spot information, the dangerous spot not having prescribed latitude; means for determining whether the chip size information and the dangerous spot information satisfy evaluation conditions, respectively; and means for changing at least one of the design rule information and the process parameter information when at least one of the chip size information and the dangerous spot information is determined not to satisfy the evaluation conditions.
Claim 13
Dependent Claim
194 words
A program for setting at least one of a process parameter and a design rule for use in manufacturing a semiconductor integrated circuit, said program causing a computer to: compact a first pattern by using design rule information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit; obtain chip size information of the semiconductor integrated circuit, which relates to the second pattern; obtain a third pattern by using process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer; compare the third pattern with the second pattern to obtain a comparison result; extract a dangerous spot from the second pattern by using the comparison result to obtain dangerous spot information, the dangerous spot not having prescribed latitude; determine whether the chip size information and the dangerous spot information satisfy evaluation conditions, respectively; and change at least one of the design rule information and the process parameter information when at least one of the chip size information and the dangerous spot information is determined not to satisfy the evaluation conditions.
Claim 14
Dependent Claim
194 words
A program for setting at least one of a process parameter and a design rule for use in manufacturing a semiconductor integrated circuit, said program causing a computer to: compact a first pattern by using design rule information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit; obtain chip size information of the semiconductor integrated circuit, which relates to the second pattern; obtain a third pattern by using process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer; compare the third pattern with the second pattern to obtain a comparison result; extract a dangerous spot from the second pattern by using the comparison result to obtain dangerous spot information, the dangerous spot not having prescribed latitude; determine whether the chip size information and the dangerous spot information satisfy evaluation conditions, respectively; and change at least one of the design rule information and the process parameter information when at least one of the chip size information and the dangerous spot information is determined not to satisfy the evaluation conditions.
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