US6622059B1
Expired / Lapsed
US
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Automated process monitoring and analysis system for semiconductor processing
Assignee: GlobalFoundries Inc
•
Filing: 2000-04-13
•
Granted: 2003-09-16
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Expires: 2020-04-13
Abstract
Abstract A method is provided for manufacturing, the method comprising processing a workpiece, measuring a parameter characteristic of the processing, and forming an output signal corresponding to the characteristic parameter measured by using the characteristic parameter measured as an input to a transistor model. The method also comprises predicting a wafer electrical test (WET) resulting value based on the output signal, detecting faulty processing based on the predicted WET resulting value, and correcting the faulty processing.
Inventors
- 👤 Anthony John Toprac
- 👤 Michael L. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:27
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/70605; G03F7/70616; G03F7/70625; H; H10; H10P; H10P74/00; G03F7/70633; H10P74/23
Claims Analysis
Total Claims: 48
Claim 1
Independent Claim
71 words
A method of manufacturing, the method comprising: processing a workpiece; measuring a parameter characteristic of the processing; forming an output signal corresponding to the characteristic parameter measured by using the characteristic parameter measured as an input to a partial least squares transistor model; predicting a wafer electrical test (WET) resulting value based on the output signal; detecting faulty processing based on the predicted WET resulting value; and correcting the faulty processing.
Claim 2
Independent Claim
71 words
A method of manufacturing, the method comprising: processing a workpiece; measuring a parameter characteristic of the processing; forming an output signal corresponding to the characteristic parameter measured by using the characteristic parameter measured as an input to a partial least squares transistor model; predicting a wafer electrical test (WET) resulting value based on the output signal; detecting faulty processing based on the predicted WET resulting value; and correcting the faulty processing.
Claim 3
Dependent Claim
48 words
The method of claim 1 , wherein using the characteristic parameter measured as the input to the partial least squares transistor model comprises using the partial least squares transistor model to map a set of in-line process metrology input values to a set of WET measurement output values.
Claim 4
Dependent Claim
70 words
The method of claim 2 , wherein using the partial least squares transistor model to map the set of the in-line process metrology input values to the set of the WET measurement output values comprises using the partial least squares transistor model to define at least a subset of the in-line process metrology input values having a significant effect on at least a subset of the WET measurement output values.
Claim 5
Dependent Claim
37 words
The method of claim 3 , wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.
Claim 6
Dependent Claim
48 words
The method of claim 4 , wherein inverting the transistor model to define the change in the processing comprises defining a change in a critical dimension of a feature formed in the processing needed to bring the subsequent predicted WET resulting values within the range of specification values.
Claim 7
Dependent Claim
47 words
The method of claim 5 , wherein defining the change in the critical dimension of the feature formed in the processing comprises defining the change in the critical dimension of at least one of a poly gate line width and a spacer width of an MOS transistor.
Claim 8
Dependent Claim
52 words
The method of claim 5 , wherein defining the change in the critical dimension of the feature formed in the processing comprises defining the change in the critical dimension of at least one of a poly gate line thickness, a gate dielectric thickness and a silicide layer thickness of an MOS transistor.
Claim 9
Dependent Claim
48 words
The method of claim 4 , wherein inverting the transistor model to define the change in the processing comprises defining a change in a doping level of a feature formed in the processing needed to bring the subsequent predicted WET resulting values within the range of specification values.
Claim 10
Dependent Claim
37 words
The method of claim 8 , wherein defining the change in the doping level of the feature formed in the processing comprises defining the change in the doping level of a source/drain region of an MOS transistor.
Claim 11
Dependent Claim
39 words
The method of claim 8 , wherein defining the change in the doping level of the feature formed in the processing comprises defining the change in the doping level of a source/drain extension (SDE) region of an MOS transistor.
Claim 12
Dependent Claim
37 words
The method of claim 2 , wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.
Claim 13
Dependent Claim
48 words
The method of claim 11 , wherein inverting the transistor model to define the change in the processing comprises defining a change in a critical dimension of a feature formed in the processing needed to bring the subsequent predicted WET resulting values within the range of specification values.
Claim 14
Dependent Claim
47 words
The method of claim 12 , wherein defining the change in the critical dimension of the feature formed in the processing comprises defining the change in the critical dimension of at least one of a poly gate line width and a spacer width of an MOS transistor.
Claim 15
Dependent Claim
52 words
The method of claim 12 , wherein defining the change in the critical dimension of the feature formed in the processing comprises defining the change in the critical dimension of at least one of a poly gate line thickness, a gate dielectric thickness and a silicide layer thickness of an MOS transistor.
Claim 16
Dependent Claim
48 words
The method of claim 11 , wherein inverting the transistor model to define the change in the processing comprises defining a change in a doping level of a feature formed in the processing needed to bring the subsequent predicted WET resulting values within the range of specification values.
Claim 17
Dependent Claim
37 words
The method of claim 15 , wherein defining the change in the doping level of the feature formed in the processing comprises defining the change in the doping level of a source/drain region of an MOS transistor.
Claim 18
Dependent Claim
39 words
The method of claim 15 , wherein defining the change in the doping level of the feature formed in the processing comprises defining the change in the doping level of a source/drain extension (SDE) region of an MOS transistor.
Claim 19
Dependent Claim
37 words
The method of claim 1 , wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.
Claim 20
Dependent Claim
48 words
The method of claim 18 , wherein inverting the transistor model to define the change in the processing comprises defining a change in a critical dimension of a feature formed in the processing needed to bring the subsequent predicted WET resulting values within the range of specification values.
Claim 21
Dependent Claim
47 words
The method of claim 19 , wherein defining the change in the critical dimension of the feature formed in the processing comprises defining the change in the critical dimension of at least one of a poly gate line width and a spacer width of an MOS transistor.
Claim 22
Dependent Claim
52 words
The method of claim 19 , wherein defining the change in the critical dimension of the feature formed in the processing comprises defining the change in the critical dimension of at least one of a poly gate line thickness, a gate dielectric thickness and a silicide layer thickness of an MOS transistor.
Claim 23
Dependent Claim
48 words
The method of claim 18 , wherein inverting the transistor model to define the change in the processing comprises defining a change in a doping level of a feature formed in the processing needed to bring the subsequent predicted WET resulting values within the range of specification values.
Claim 24
Dependent Claim
37 words
The method of claim 22 , wherein defining the change in the doping level of the feature formed in the processing comprises defining the change in the doping level of a source/drain region of an MOS transistor.
Claim 25
Dependent Claim
39 words
The method of claim 22 , wherein defining the change in the doping level of the feature formed in the processing comprises defining the change in the doping level of a source/drain extension (SDE) region of an MOS transistor.
Claim 26
Dependent Claim
92 words
A computer-readable, program storage device encoded with instructions that, when executed by a computer, perform a method for manufacturing a workpiece, the method comprising: processing the workpiece; measuring a parameter characteristic of the processing performed on the workpiece; forming an output signal corresponding to the characteristic parameter measured by using the characteristic parameter measured as an input to a partial least squares transistor model; predicting a wafer electrical test (WET) resulting value based on the output signal; detecting faulty processing based on the predicted WET resulting value; and correcting the faulty processing.
Claim 27
Dependent Claim
92 words
A computer-readable, program storage device encoded with instructions that, when executed by a computer, perform a method for manufacturing a workpiece, the method comprising: processing the workpiece; measuring a parameter characteristic of the processing performed on the workpiece; forming an output signal corresponding to the characteristic parameter measured by using the characteristic parameter measured as an input to a partial least squares transistor model; predicting a wafer electrical test (WET) resulting value based on the output signal; detecting faulty processing based on the predicted WET resulting value; and correcting the faulty processing.
Claim 28
Dependent Claim
51 words
The computer-readable, program storage device of claim 25 , wherein using the characteristic parameter measured as the input to the partial least squares transistor model comprises using the partial least squares transistor model to map a set of in-line process metrology input values to a set of WET measurement output values.
Claim 29
Dependent Claim
73 words
The computer-readable, program storage device of claim 26 , wherein using the partial least squares transistor model to map the set of the in-line process metrology input values to the set of the WET measurement output values comprises using the partial least squares transistor model to define at least a subset of the in-line process metrology input values having a significant effect on at least a subset of the WET measurement output values.
Claim 30
Dependent Claim
40 words
The computer-readable, program storage device of claim 27 , wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.
Claim 31
Dependent Claim
40 words
The computer-readable, program storage device of claim 26 , wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.
Claim 32
Dependent Claim
40 words
The computer-readable, program storage device of claim 25 , wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.
Claim 33
Dependent Claim
80 words
A computer programmed to perform a method of manufacturing, the method comprising: processing a workpiece; measuring a parameter characteristic of the processing performed on the workpiece; forming an output signal corresponding to the characteristic parameter measured by using the characteristic parameter measured as an input to a partial least squares transistor model; predicting a wafer electrical test (WET) resulting value based on the output signal; detecting faulty processing based on the predicted WET resulting value; and correcting the faulty processing.
Claim 34
Dependent Claim
80 words
A computer programmed to perform a method of manufacturing, the method comprising: processing a workpiece; measuring a parameter characteristic of the processing performed on the workpiece; forming an output signal corresponding to the characteristic parameter measured by using the characteristic parameter measured as an input to a partial least squares transistor model; predicting a wafer electrical test (WET) resulting value based on the output signal; detecting faulty processing based on the predicted WET resulting value; and correcting the faulty processing.
Claim 35
Dependent Claim
48 words
The computer of claim 31 , wherein using the characteristic parameter measured as the input to the partial least squares transistor model comprises using the partial least squares transistor model to map a set of in-line process metrology input values to a set of WET measurement output values.
Claim 36
Dependent Claim
70 words
The computer of claim 32 , wherein using the partial least squares transistor model to map the set of the in-line process metrology input values to the set of the WET measurement output values comprises using the partial least squares transistor model to define at least a subset of the in-line process metrology input values having a significant effect on at least a subset of the WET measurement output values.
Claim 37
Dependent Claim
37 words
The computer of claim 33 , wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.
Claim 38
Dependent Claim
37 words
The computer of claim 32 , wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.
Claim 39
Dependent Claim
37 words
The computer of claim 31 , wherein correcting the faulty processing comprises inverting the transistor model to define a change in the processing needed to bring subsequent predicted WET resulting values within a range of specification values.
Claim 40
Independent Claim
97 words
A method of manufacturing, the method comprising: forming a plurality of structures on a workpiece using an in-line process metrology tool having at least one input value in a processing step; measuring a parameter characteristic of the plurality of structures; forming an output signal using the measured characteristic parameter and the at least one input value as inputs to a partial least squares transistor model; predicting a wafer electrical test (WET) resulting value based on the output signal; detecting faulty processing in the processing step based on the predicted WET resulting value; and correcting the faulty processing.
Claim 41
Independent Claim
97 words
A method of manufacturing, the method comprising: forming a plurality of structures on a workpiece using an in-line process metrology tool having at least one input value in a processing step; measuring a parameter characteristic of the plurality of structures; forming an output signal using the measured characteristic parameter and the at least one input value as inputs to a partial least squares transistor model; predicting a wafer electrical test (WET) resulting value based on the output signal; detecting faulty processing in the processing step based on the predicted WET resulting value; and correcting the faulty processing.
Claim 42
Dependent Claim
32 words
The method of claim 37 , wherein forming the output signal comprises using the partial least squares transistor model to map the input values to a set of WET measurement output values.
Claim 43
Dependent Claim
60 words
The method of claim 38 , wherein using the partial least squares transistor model to map the input values to the set of WET measurement output values comprises using the partial least squares transistor model to define at least a subset of the input values having a significant effect on at least a subset of the WET measurement output values.
Claim 44
Dependent Claim
41 words
The method of claim 37 , wherein correcting the faulty processing comprises inverting the partial least squares transistor model to define a change in the processing step needed to bring subsequent predicted WET resulting values within a range of specification values.
Claim 45
Dependent Claim
53 words
The method of claim 40 , wherein inverting the partial least squares transistor model to define the change in the processing step comprises defining a change in a critical dimension of a feature formed in the processing step needed to bring the subsequent predicted WET resulting values within the range of specification values.
Claim 46
Dependent Claim
65 words
The method of claim 41 , wherein defining the change in the critical dimension of the feature formed in the processing step comprises defining the change in the critical dimension of at least one of a poly gate line width, a spacer width of an MOS transistor, a poly gate line thickness, a gate dielectric thickness, and a silicide layer thickness of an MOS transistor.
Claim 47
Dependent Claim
53 words
The method of claim 40 , wherein inverting the partial least squares transistor model to define the change in the processing step comprises defining a change in a doping level of a feature formed in the processing step needed to bring the subsequent predicted WET resulting values within the range of specification values.
Claim 48
Dependent Claim
48 words
The method of claim 43 , wherein defining the change in the doping level of the feature formed in the processing step comprises defining the change in the doping level of a source/drain region of an MOS transistor or a source/drain extension (SDE) region of an MOS transistor.
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