US5866437A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic process window control using simulated wet data from current and previous layer data
Assignee: GlobalFoundries Inc
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Filing: 1997-12-05
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Granted: 1999-02-02
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Expires: 2017-12-05
Abstract
Abstract A method of manufacturing semiconductor wafers using a simulation tool to determine predicted wafer electrical test measurements. The simulation tool combines in-line critical dimensions from previous from previous processes run on the current wafer lot, data from previous lots for processes subsequent to the process being run on the current lot and calibration simulation data obtained from the comparison of the predicted wafer electrical test measurements and collected wafer electrical test measurements taken from previous actual wafer electrical test measurements.
Inventors
- 👤 Ming Chun Chen
- 👤 Paul J. Steffan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:05
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/70605; G03F7/70616; G03F7/70625; H; H10; H10P; H10P74/00; H10P74/23
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
151 words
A method of manufacturing semiconductor wafers, the method comprising: starting a wafer lot in a first process of a manufacturing process; setting process parameters for the first process and running the first process; measuring in-line critical dimensions after completion of the first process; determining predicted wafer electrical test measurements by combining in-line critical dimensions from previous processes run on the wafer lot, data from previous lots for processes to be run subsequent to the process being run on the wafer lot and calibration simulation data obtained from a comparison of the predicted wafer electrical test measurements and collected actual wafer electrical test measurements taken from previous wafer electrical test measurements; determining if the predicted wafer electrical test measurements are within established wafer electrical test measurement specifications; and if the predicted wafer electrical test measurements are within the established wafer electric test measurement specifications sending the wafer lot to the next process.
Claim 2
Independent Claim
151 words
A method of manufacturing semiconductor wafers, the method comprising: starting a wafer lot in a first process of a manufacturing process; setting process parameters for the first process and running the first process; measuring in-line critical dimensions after completion of the first process; determining predicted wafer electrical test measurements by combining in-line critical dimensions from previous processes run on the wafer lot, data from previous lots for processes to be run subsequent to the process being run on the wafer lot and calibration simulation data obtained from a comparison of the predicted wafer electrical test measurements and collected actual wafer electrical test measurements taken from previous wafer electrical test measurements; determining if the predicted wafer electrical test measurements are within established wafer electrical test measurement specifications; and if the predicted wafer electrical test measurements are within the established wafer electric test measurement specifications sending the wafer lot to the next process.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-01 | 2002-08-03 | 2003-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-01 | 2006-08-03 | 2007-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-01 | 2010-08-03 | 2011-02-02 | $7700.00 | Window Closed / Lapsed |