US7105868B2
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High-electron mobility transistor with zinc oxide
Assignee: Nause Catherine D
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Filing: 2003-06-24
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Granted: 2006-09-12
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Expires: 2023-06-24
Abstract
Abstract A zinc oxide (ZnO) field effect transistor exhibits large input amplitude by using a gate insulating layer. A channel layer and the gate insulating layer are sequentially laminated on a substrate. A gate electrode is formed on the gate insulating layer. A source contact and a drain contact are disposed at the both sides of the gate contact and are electrically connected to the channel layer via openings. The channel layer is formed from n-type ZnO. The gate insulating layer is made from aluminum nitride/aluminum gallium nitride (AlN/AlGaN) or magnesium zinc oxide (MgZnO), which exhibits excellent insulation characteristics, thus increasing the Schottky barrier and achieving large input amplitude. If the FET is operated in the enhancement mode, it is operable in a manner similar to a silicon metal oxide semiconductor field effect transistor (Si-MOS-type FET), resulting in the formation of an inversion layer.
Inventors
- 👤 Jeff Nause
- 👤 Shanthi Ganesan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:46
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/86; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D62/82; H10D62/85; H10D62/8503
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
109 words
A high electron mobility transistor (HEMT) comprising: a channel layer being composed of a II-VI compound semiconductor zinc oxide (ZnO); a gate contact disposed in proximity to, but not in contact with, said channel layer; and a gate insulating layer disposed between and in contact with said gate contact and said channel layer and composed of at least one of a Group-III nitride compound semiconductor and a magnesium zinc oxide (MgZnO) quantum well structure, said gate insulating layer having side walls, said gate contact positioned between the sidewalls of said gate insulating layer so that sides of said gate contact face the side walls of said gate insulating layer.
Claim 2
Dependent Claim
109 words
A high electron mobility transistor (HEMT) comprising: a channel layer being composed of a II-VI compound semiconductor zinc oxide (ZnO); a gate contact disposed in proximity to, but not in contact with, said channel layer; and a gate insulating layer disposed between and in contact with said gate contact and said channel layer and composed of at least one of a Group-III nitride compound semiconductor and a magnesium zinc oxide (MgZnO) quantum well structure, said gate insulating layer having side walls, said gate contact positioned between the sidewalls of said gate insulating layer so that sides of said gate contact face the side walls of said gate insulating layer.
Claim 3
Dependent Claim
31 words
A HEMT according to claim 1 wherein said gate insulating layer is composed of at least one of an epitaxially grown Group-III nitride compound semiconductor and a MgZnO quantum well structure.
Claim 4
Dependent Claim
21 words
A HEMT according to claim 2 wherein said channel layer is composed of an epitaxially grown Group-II-VI zinc oxide compound semiconductor.
Claim 5
Dependent Claim
36 words
A HEMT according to claim 1 wherein said gate insulating layer is composed of a Group-III compound semiconductor expressed by a chemical formula Al x Ga 1−x N (0.3<x≦1) or Mg x Zn 1−x O (0.1<x<0.4).
Claim 6
Dependent Claim
46 words
A HEMT according to claim 1 wherein said channel layer is formed on a substrate comprising at least one of zinc oxide (ZnO), silicon carbide (SiC), sapphire (Al 2 O 3 ), and silicon (Si) and has a bulk resistivity higher than 10 5 ohm-centimeter (Ω-cm).
Claim 7
Dependent Claim
22 words
A HEMT according to claim 1 wherein the thickness of said gate insulating layer ranges from 0.30 nanometer (nm) to 50 nm.
Claim 8
Dependent Claim
55 words
A HEMT according to claim 1 wherein said HEMT employs piezoelectric doping created by strain due to lattice mismatch between the channel layer and the gate insulating layer that produces a two-dimensional electron gas (2DEG) near an interface between the channel layer and the gate insulating layer to avoid usage of a conventional doping method.
Claim 9
Dependent Claim
37 words
A HEMT according to claim 1 wherein said gate contact is selected from the group consisting of titanium (Ti), platinum (Pt), silver (Ag), gold (Au), chromium (Cr), alloys of titanium(Ti) and tungsten (W), and platinum silicide (PtSi).
Claim 10
Dependent Claim
28 words
A HEMT according to claim 1 wherein source and drain contacts to said channel layer comprise an alloy of titanium (Ti), silicon (Si), aluminum (Al) and nickel (Ni).
Claim 11
Dependent Claim
26 words
A HEMT according to claim 1 and further comprising a passivation layer on said gate contact and said source and drain contacts to said channel layer.
Claim 12
Dependent Claim
27 words
A HEMT according to claim 1 wherein an area of said gate contact with said gate insulating layer is decreased due to the presence of said sidewalls.
Claim 13
Dependent Claim
24 words
A HEMT according to claim 1 wherein the channel layer is composed of ZnO and is grown by metal organic chemical vapor deposition (MOCVD).
Claim 14
Dependent Claim
42 words
A HEMT according to claim 1 wherein gate insulating layer is grown by metal organic chemical vapor deposition (MOCVD) and sequentially laminated on said channel layer, the HEMT further comprising: a substrate composed of ZnO, the channel layer laminated onto the substrate.
Claim 15
Dependent Claim
13 words
A HEMT according to claim 13 wherein the substrate is a c-surface substrate.
Claim 16
Independent Claim
111 words
A method comprising the steps of: defining a channel layer composed of a II-VI compound semiconductor zinc oxide (ZnO); forming a gate insulating layer in contact with said channel layer and composed of at least one of a Group-III nitride compound semiconductor and a magnesium zinc oxide (MgZnO) quantum well structure, said gate insulating layer formed with side walls; and forming a gate contact disposed on and in contact with said gate insulating layer and positioned between said side walls, said gate contact formed to have sides facing said side walls of said gate insulating layer, said gate contact formed in proximity to, but not in contact with, said channel layer.
Claim 17
Independent Claim
111 words
A method comprising the steps of: defining a channel layer composed of a II-VI compound semiconductor zinc oxide (ZnO); forming a gate insulating layer in contact with said channel layer and composed of at least one of a Group-III nitride compound semiconductor and a magnesium zinc oxide (MgZnO) quantum well structure, said gate insulating layer formed with side walls; and forming a gate contact disposed on and in contact with said gate insulating layer and positioned between said side walls, said gate contact formed to have sides facing said side walls of said gate insulating layer, said gate contact formed in proximity to, but not in contact with, said channel layer.
Claim 18
Dependent Claim
20 words
A method according to claim 15 wherein the gate insulating layer is formed by metal organic chemical vapor deposition (MOCVD).
Claim 19
Dependent Claim
17 words
A method according to claim 15 wherein the channel layer is formed on a c-surface ZnO substrate.
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