US6429467B1
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Heterojunction field effect transistor
Assignee: NEC Corp
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Filing: 2000-01-27
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Granted: 2002-08-06
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Expires: 2020-01-27
Abstract
Abstract A heterojunction field effect transistor has a buffer layer, a channel layer, a gate insulating layer, a source electrode, a drain electrode, and a gate electrode to be in contact with a substrate. The buffer layer has at least one GaN layer. The channel layer has a composition of InzGa1-zN (0<=z<1) and the gate insulating layer is an InAlGaN layer. The source and drain electrodes are in ohmic contact with the channel layer and the gate electrode and the gate insulating layer are in Schottky contact with each other.
Inventors
- 👤 Yuji Ando
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:09
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/801; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D30/4755; H10D62/00; H10D62/80; H10D62/85; H10D62/8503
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
104 words
A heterojunction field effect transistor having a buffer layer comprising at least one GaN layer, a channel layer, a gate insulating layer, a source electrode, a drain electrode, and a gate electrode, to be in contact with a substrate, wherein said channel layer has a composition of In z Ga 1−z N(0≦z<1) and said gate insulating layer is an In x Al y Ga 1−x−y N layer, wherein y is less than approximately 4.66x, and said source and drain electrodes are in ohmic contact with said channel layer and said gate electrode and said gate insulating layer are in Schottky contact with each other.
Claim 2
Dependent Claim
104 words
A heterojunction field effect transistor having a buffer layer comprising at least one GaN layer, a channel layer, a gate insulating layer, a source electrode, a drain electrode, and a gate electrode, to be in contact with a substrate, wherein said channel layer has a composition of In z Ga 1−z N(0≦z<1) and said gate insulating layer is an In x Al y Ga 1−x−y N layer, wherein y is less than approximately 4.66x, and said source and drain electrodes are in ohmic contact with said channel layer and said gate electrode and said gate insulating layer are in Schottky contact with each other.
Claim 3
Dependent Claim
125 words
A heterojunction field effect transistor having a buffer layer comprising at least one GaN layer, a channel layer, a gate insulating layer, a source electrode, a drain electrode, and a gate electrode, to be in contact with a substrate, wherein said channel layer has a composition of In z Ga 1−z N (0≦z<1) and said gate insulating layer is an InAlGaN layer, and said source and drain electrodes are in ohmic contact with said channel layer and said gate electrode and said gate insulating layer are in Schottky contact with each other, wherein the composition of said InAlGaN layer is expressed by In x Al y Ga 1−x−y N (x>0, y>0, x+y≦1) and a composition ratio of x to y satisfies an inequality of |y−4.66x|<1.
Claim 4
Dependent Claim
125 words
A heterojunction field effect transistor having a buffer layer comprising at least one GaN layer, a channel layer, a gate insulating layer, a source electrode, a drain electrode, and a gate electrode, to be in contact with a substrate, wherein said channel layer has a composition of In z Ga 1−z N (0≦z<1) and said gate insulating layer is an InAlGaN layer, and said source and drain electrodes are in ohmic contact with said channel layer and said gate electrode and said gate insulating layer are in Schottky contact with each other, wherein the composition of said InAlGaN layer is expressed by In x Al y Ga 1−x−y N (x>0, y>0, x+y≦1) and a composition ratio of x to y satisfies an inequality of |y−4.66x|<1.
Claim 5
Dependent Claim
125 words
A heterojunction field effect transistor having a buffer layer comprising at least one GaN layer, a channel layer, a gate insulating layer, a source electrode, a drain electrode, and a gate electrode, to be in contact with a substrate, wherein said channel layer has a composition of In z Ga 1−z N (0≦z<1) and said gate insulating layer is an InAlGaN layer, and said source and drain electrodes are in ohmic contact with said channel layer and said gate electrode and said gate insulating layer are in Schottky contact with each other, wherein the composition of said InAlGaN layer is expressed by In x Al y Ga 1−x−y N (x>0, y>0, x+y≦1) and a composition ratio of x to y satisfies an inequality of |y−4.66x|<0.05.
Claim 6
Dependent Claim
125 words
A heterojunction field effect transistor having a buffer layer comprising at least one GaN layer, a channel layer, a gate insulating layer, a source electrode, a drain electrode, and a gate electrode, to be in contact with a substrate, wherein said channel layer has a composition of In z Ga 1−z N (0≦z<1) and said gate insulating layer is an InAlGaN layer, and said source and drain electrodes are in ohmic contact with said channel layer and said gate electrode and said gate insulating layer are in Schottky contact with each other, wherein the composition of said InAlGaN layer is expressed by In x Al y Ga 1−x−y N (x>0, y>0, x+y≦1) and a composition ratio of x to y satisfies an inequality of |y−4.66x|<0.05.
Claim 7
Dependent Claim
24 words
A transistor according to claim 2 , wherein a composition ratio of x to y of said InAlGaN layer satisfies an inequality of y>0.533(x−z).
Claim 8
Dependent Claim
24 words
A transistor according to claim 3 , wherein a composition ratio of x to y of said InAlGaN layer satisfies an inequality of y>0.533(x−z).
Claim 9
Dependent Claim
38 words
A transistor according to claim 1 , wherein said InAlGaN layer has a superlattice structure made of a multilayered structure of an In T Ga 1−T N layer (0<T<1) and an Al S Ga 1−S N layer (0<S<1).
Claim 10
Dependent Claim
38 words
A transistor according to claim 1 , wherein said InAlGaN layer has a superlattice structure made of a multilayered structure of an In 1−T Ga T N layer (0<T<1) and an In 1−S Al S N layer (0<S<1).
Claim 11
Dependent Claim
38 words
A transistor according to claim 1 , wherein said InAlGaN layer has a superlattice structure made of a multilayered structure of an In T Al 1−T N layer (0<T<1) and an Al 1−S Ga S N layer (0<S<1).
Claim 12
Dependent Claim
16 words
A transistor according to claim 1 , wherein said InAlGaN layer is doped with an impurity.
Claim 13
Dependent Claim
16 words
A transistor according to claim 2 , wherein said InAlGaN layer is doped with an impurity.
Claim 14
Dependent Claim
16 words
A transistor according to claim 3 , wherein said InAlGaN layer is doped with an impurity.
Claim 15
Dependent Claim
16 words
A transistor according to claim 4 , wherein said InAlGaN layer is doped with an impurity.
Claim 16
Dependent Claim
37 words
A transistor according to claim 2 , wherein said InAlGaN layer has a superlattice structure made of a multilayered structure of an In T Ga 1−T N layer(0<T<1) and an Al S Ga 1−S N layer (0<S<1).
Claim 17
Dependent Claim
38 words
A transistor according to claim 2 , wherein said InAlGaN layer has a superlattice structure made of a multilayered structure of an In 1−T Ga T N layer (0<T<1) and an In 1−S Al S N layer (0<S<1).
Claim 18
Dependent Claim
37 words
A transistor according to claim 2 , wherein said InAlGaN layer has a superlattice structure made of a multilayered structure of an In T Al 1−T N layer (0<T<1) and an Al 1−S Ga S N layer(0<S<1).
Claim 19
Dependent Claim
38 words
A transistor according to claim 3 , wherein said InAlGaN layer has a superlattice structure made of a multilayered structure of an In T Ga 1−T N layer (0<T<1) and an Al S Ga 1−S N layer (0<S<1).
Claim 20
Dependent Claim
38 words
A transistor according to claim 3 , wherein said InAlGaN layer has a superlattice structure made of a multilayered structure of an In 1−T Ga T N layer (0<T<1) and an In 1−S Al S N layer (0<S<1).
Claim 21
Dependent Claim
38 words
A transistor according to claim 3 , wherein said InAlGaN layer has a superlattice structure made of a multilayered structure of an In T Al 1−T N layer (0T<1) and an Al 1−S Ga S N layer (0<S<1).
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