Nonvolatile semiconductor storage and its manufacturing method

Claim 2

A nonvolatile semiconductor memory device having a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the floating gate through an inter-poly silicon insulator film, wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least three layers comprising a first silicon dioxide layer, a layer having nitrogen and silicon as main constituent elements, and a tantalum pentoxide layer.

Claim 3

The nonvolatile semiconductor memory device according to claim 1 , wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least four layers comprising the first silicon dioxide layer, the layer having nitrogen and silicon as the main constituent elements, the tantalum pentoxide layer, and a second silicon dioxide layer.

Claim 4

The nonvolatile semiconductor memory device according to claim 1 , wherein a density of a number of oxygen atoms included in the layer having nitrogen and silicon as the main constituent elements constituting the inter-poly silicon insulator film is smaller than a density of a number of nitrogen atoms therein.

Claim 5

The nonvolatile semiconductor memory device according to claim 1 , wherein the first silicon dioxide layer constituting the inter-poly silicon insulator film has a thickness of 5 nm or less.

Claim 6

The nonvolatile semiconductor memory device according to claim 1 , wherein the layer having nitrogen and silicon as the main constituent elements constituting the inter-poly silicon insulator film has a thickness of 1.5 nm or more.

Claim 7

The nonvolatile semiconductor memory device according to claim 2 , wherein the second silicon dioxide layer constituting the inter-poly silicon insulator film has a thickness of 2 nm or more.

Claim 8

A nonvolatile semiconductor memory device having a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the floating gate through an inter-poly silicon insulator film, wherein the inter-poly silicon insulator film is constituted from a multilayer film and at least one layer of the multilayer film is a tantalum pentoxide layer with a dielectric constant of 50 or more.

Claim 9

A nonvolatile semiconductor memory device having a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the floating gate through an inter-poly silicon insulator film, wherein the inter-poly silicon insulator film is constituted from a multilayer film and at least one layer of the multilayer film is a tantalum pentoxide layer with a dielectric constant of 50 or more.

Claim 10

The nonvolatile semiconductor memory device according to claim 7 , wherein the tantalum pentoxide layer contacts floating gates through a layer including at least a silicon dioxide layer.

Claim 11

The nonvolatile semiconductor memory device according to claim 8 , wherein the layer including the silicon dioxide layer constituting the inter-poly silicon insulator film includes nitrogen.

Claim 12

The nonvolatile semiconductor memory device according to claim 7 , wherein the tantalum pentoxide layer contacts control gates through a layer including at least a silicon dioxide layer.

Claim 13

A nonvolatile semiconductor memory device comprising: a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the floating gate through an inter-poly silicon insulator film; and a peripheral circuit area having a plurality of second MOS field effect transistors disposed therein, each of the second MOS field effect transistors comprising a second well region formed in the semiconductor substrate, a second diffusion layer formed in the second well region, for functioning as a source or a drain, and a gate electrode formed over the second well region through a gate insulator film; wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least a tantalum pentoxide layer, and a thickness of poly silicon of gate electrodes in the peripheral circuit area is formed to be equal to a thickness of poly silicon constituting control gates in the memory array area.

Claim 14

A nonvolatile semiconductor memory device comprising: a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the floating gate through an inter-poly silicon insulator film; and a peripheral circuit area having a plurality of second MOS field effect transistors disposed therein, each of the second MOS field effect transistors comprising a second well region formed in the semiconductor substrate, a second diffusion layer formed in the second well region, for functioning as a source or a drain, and a gate electrode formed over the second well region through a gate insulator film; wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least a tantalum pentoxide layer, and a thickness of poly silicon of gate electrodes in the peripheral circuit area is formed to be equal to a thickness of poly silicon constituting control gates in the memory array area.

Claim 15

A nonvolatile semiconductor memory device comprising: a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the floating gate through an inter-poly silicon insulator film; and a peripheral circuit area having a plurality of second MOS field effect transistors disposed therein, each of the second MOS field effect transistors comprising a second well region formed in the semiconductor substrate, a second diffusion layer formed in the second well region, for functioning as a source or a drain, and a gate electrode formed over the second well region through a gate insulator film; wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least a tantalum pentoxide layer, and at least a part of the second MOS field effect transistors use the multilayer film including the tantalum pentoxide layer as gate insulator films.

Claim 16

A nonvolatile semiconductor memory device comprising: a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the floating gate through an inter-poly silicon insulator film; and a peripheral circuit area having a plurality of second MOS field effect transistors disposed therein, each of the second MOS field effect transistors comprising a second well region formed in the semiconductor substrate, a second diffusion layer formed in the second well region, for functioning as a source or a drain, and a gate electrode formed over the second well region through a gate insulator film; wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least a tantalum pentoxide layer, and at least a part of the second MOS field effect transistors use the multilayer film including the tantalum pentoxide layer as gate insulator films.

Claim 17

A nonvolatile semiconductor memory device comprising a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a first floating gate formed over the first well region through a tunnel dielectric, a second floating gate electrically connected over to the first floating gate, and a control gate formed over the second floating gate through an inter-poly silicon insulator film, wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least three layers comprising a first silicon dioxide layer, a layer having nitrogen and silicon as main constituent elements, and a tantalum pentoxide layer.

Claim 18

A nonvolatile semiconductor memory device comprising a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a first floating gate formed over the first well region through a tunnel dielectric, a second floating gate electrically connected over to the first floating gate, and a control gate formed over the second floating gate through an inter-poly silicon insulator film, wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least three layers comprising a first silicon dioxide layer, a layer having nitrogen and silicon as main constituent elements, and a tantalum pentoxide layer.

Claim 19

The nonvolatile semiconductor memory device according to claim 13 , wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least four layers comprising the first silicon dioxide layer, the layer having nitrogen and silicon as the main constituent elements, the tantalum pentoxide layer, and a second silicon dioxide layer.

Claim 20

The nonvolatile semiconductor memory device according to claim 13 , wherein a density of a number of oxygen atoms included in the layer having nitrogen and silicon as the main constituent elements constituting the inter-poly silicon insulator film is smaller than a density of a number of nitrogen atoms therein.

Claim 21

The nonvolatile semiconductor memory device according to claim 13 , wherein the first silicon dioxide layer constituting the inter-poly silicon insulator film has a thickness of 5 nm or less.

Claim 22

The nonvolatile semiconductor memory device according to claim 13 , wherein the layer having nitrogen and silicon as the main constituent elements constituting the inter-poly silicon insulator film has a thickness of 1.5 nm or more.

Claim 23

The nonvolatile semiconductor memory device according to claim 14 , wherein the second silicon dioxide layer constituting the inter-poly silicon insulator film has a thickness of 2 nm or more.

Claim 24

A nonvolatile semiconductor memory device having a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a first floating gate formed over the first well region through a tunnel dielectric, a second floating gate electrically connected over to the first floating gate, and a control gate formed over the second floating gate through an inter-poly silicon insulator film, wherein the inter-poly silicon insulator film is constituted from a multilayer film and at least one layer of the multilayer film is a tantalum pentoxide layer with a dielectric constant of 50 or more.

Claim 25

A nonvolatile semiconductor memory device having a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a first floating gate formed over the first well region through a tunnel dielectric, a second floating gate electrically connected over to the first floating gate, and a control gate formed over the second floating gate through an inter-poly silicon insulator film, wherein the inter-poly silicon insulator film is constituted from a multilayer film and at least one layer of the multilayer film is a tantalum pentoxide layer with a dielectric constant of 50 or more.

Claim 26

The nonvolatile semiconductor memory device according to claim 19 , wherein the tantalum pentoxide layer contacts floating gates through a layer including at least a silicon dioxide layer.

Claim 27

The nonvolatile semiconductor memory device according to claim 20 , wherein the layer including the silicon dioxide layer constituting the inter-poly silicon insulator film includes nitrogen.

Claim 28

The nonvolatile semiconductor memory device according to claim 19 , wherein the tantalum pentoxide layer contacts control gates through a layer including a silicon dioxide layer.

Claim 29

A nonvolatile semiconductor memory device comprising: a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a first floating gate formed over the first well region through a tunnel dielectric, a second floating gate electrically connected over to the first floating gate, and a control gate formed over the second floating gate through an inter-poly silicon insulator film; and a peripheral circuit area having a plurality of second MOS field effect transistors disposed therein, each of the second MOS field effect transistors comprising a second well region formed in the semiconductor substrate, a second diffusion layer formed in the second well region, for functioning as a source or a drain, and a gate electrode formed over the second well region through a gate insulator film; wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least a tantalum pentoxide layer, and a film thickness of poly silicon of gate electrodes in the peripheral circuit area is formed to be equal to a film thickness of poly silicon constituting control gates in the memory array area.

Claim 30

A nonvolatile semiconductor memory device comprising: a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a first floating gate formed over the first well region through a tunnel dielectric, a second floating gate electrically connected over to the first floating gate, and a control gate formed over the second floating gate through an inter-poly silicon insulator film; and a peripheral circuit area having a plurality of second MOS field effect transistors disposed therein, each of the second MOS field effect transistors comprising a second well region formed in the semiconductor substrate, a second diffusion layer formed in the second well region, for functioning as a source or a drain, and a gate electrode formed over the second well region through a gate insulator film; wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least a tantalum pentoxide layer, and a film thickness of poly silicon of gate electrodes in the peripheral circuit area is formed to be equal to a film thickness of poly silicon constituting control gates in the memory array area.

Claim 31

A nonvolatile semiconductor memory device comprising: a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a first floating gate formed over the first well region through a tunnel dielectric, a second floating gate electrically connected over to the first floating gate, and a control gate formed over the second floating gate through an inter-poly silicon insulator film; and a peripheral circuit area having a plurality of second MOS field effect transistors disposed therein, each of the second MOS field effect transistors comprising a second well region formed in the semiconductor substrate, a second diffusion layer formed in the second well region, for functioning as a source or a drain, and a gate electrode formed over the second well region through a gate insulator film; wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least a tantalum pentoxide layer, and at least a part of the second MOS field effect transistors use the multilayer film including the tantalum pentoxide layer as gate insulator films.

Claim 32

A nonvolatile semiconductor memory device comprising: a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a first floating gate formed over the first well region through a tunnel dielectric, a second floating gate electrically connected over to the first floating gate, and a control gate formed over the second floating gate through an inter-poly silicon insulator film; and a peripheral circuit area having a plurality of second MOS field effect transistors disposed therein, each of the second MOS field effect transistors comprising a second well region formed in the semiconductor substrate, a second diffusion layer formed in the second well region, for functioning as a source or a drain, and a gate electrode formed over the second well region through a gate insulator film; wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least a tantalum pentoxide layer, and at least a part of the second MOS field effect transistors use the multilayer film including the tantalum pentoxide layer as gate insulator films.

Claim 33

A nonvolatile semiconductor memory device having a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the first well region and the floating gate through an inter-poly silicon insulator film, wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least three layers comprising a first silicon dioxide layer, a layer having nitrogen and silicon as main constituent elements, and a tantalum pentoxide layer.

Claim 34

A nonvolatile semiconductor memory device having a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the first well region and the floating gate through an inter-poly silicon insulator film, wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least three layers comprising a first silicon dioxide layer, a layer having nitrogen and silicon as main constituent elements, and a tantalum pentoxide layer.

Claim 35

The nonvolatile semiconductor memory device according to claim 25 , wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least four layers comprising the first silicon dioxide layer, the layer having nitrogen and silicon as the main constituent elements, the tantalum pentoxide layer, and a second silicon dioxide layer.

Claim 36

The nonvolatile semiconductor memory device according to claim 25 , wherein a density of a number of oxygen atoms included in the layer having nitrogen and silicon as the main constituent elements constituting the inter-poly silicon insulator film is smaller than a density of a number of nitrogen atoms therein.

Claim 37

The nonvolatile semiconductor memory device according to claim 25 , wherein the first silicon dioxide layer constituting the inter-poly silicon insulator film has a thickness of 5 nm or less.

Claim 38

The nonvolatile semiconductor memory device according to claim 25 , wherein the layer having nitrogen and silicon as the main constituent elements constituting the inter-poly silicon insulator film has a thickness of 1.5 nm or more.

Claim 39

The nonvolatile semiconductor memory device according to claim 26 , wherein the second silicon dioxide layer constituting the inter-poly silicon insulator film has a thickness of 2 nm or more.

Claim 40

A nonvolatile semiconductor memory device having a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the first well and the floating gate through an inter-poly silicon insulator film, wherein the inter-poly silicon insulator film is constituted from a multilayer film and at least one layer of the multilayer film is a tantalum pentoxide layer with a dielectric constant of 50 or more.

Claim 41

A nonvolatile semiconductor memory device having a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the first well and the floating gate through an inter-poly silicon insulator film, wherein the inter-poly silicon insulator film is constituted from a multilayer film and at least one layer of the multilayer film is a tantalum pentoxide layer with a dielectric constant of 50 or more.

Claim 42

The nonvolatile semiconductor memory device according to claim 31 , wherein the tantalum pentoxide layer contacts floating gates through a layer including at least a silicon dioxide layer.

Claim 43

The nonvolatile memory device according to claim 32 , wherein the layer including the silicon dioxide layer constituting the inter-poly silicon insulator film includes nitrogen.

Claim 44

The nonvolatile memory device according to claim 31 , wherein the tantalum pentoxide layer contacts control gates through a layer including at least a silicon dioxide layer.

Claim 45

A nonvolatile semiconductor memory device comprising: a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the first well region and the floating gate through an inter-poly silicon insulator film; and a peripheral circuit area having a plurality of second MOS field effect transistors disposed therein, each of the second MOS field effect transistors comprising a second well region formed in the semiconductor substrate, a second diffusion layer formed in the second well region, for functioning as a source or a drain, and a gate electrode formed over the second well region through a gate insulator film; wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least a tantalum pentoxide layer, and a film thickness of poly silicon of gate electrodes in the peripheral circuit area is formed to be equal to a film thickness of poly silicon constituting control gates in the memory array area.

Claim 46

A nonvolatile semiconductor memory device comprising: a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the first well region and the floating gate through an inter-poly silicon insulator film; and a peripheral circuit area having a plurality of second MOS field effect transistors disposed therein, each of the second MOS field effect transistors comprising a second well region formed in the semiconductor substrate, a second diffusion layer formed in the second well region, for functioning as a source or a drain, and a gate electrode formed over the second well region through a gate insulator film; wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least a tantalum pentoxide layer, and a film thickness of poly silicon of gate electrodes in the peripheral circuit area is formed to be equal to a film thickness of poly silicon constituting control gates in the memory array area.

Claim 47

A nonvolatile semiconductor memory device comprising: a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the first well and the floating gate through an inter-poly silicon insulator film; and a peripheral circuit area having a plurality of second MOS field effect transistors disposed therein, each of the second MOS field effect transistors comprising a second well region formed in the semiconductor substrate, a second diffusion layer formed in the second well region, for functioning as a source or a drain, and a gate electrode formed over the second well region through a gate insulator film; wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least a tantalum pentoxide layer, and at least a part of the second MOS field effect transistors use the multilayer film including the tantalum pentoxide layer as gate insulator films.

Claim 48

A nonvolatile semiconductor memory device comprising: a memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the first well and the floating gate through an inter-poly silicon insulator film; and a peripheral circuit area having a plurality of second MOS field effect transistors disposed therein, each of the second MOS field effect transistors comprising a second well region formed in the semiconductor substrate, a second diffusion layer formed in the second well region, for functioning as a source or a drain, and a gate electrode formed over the second well region through a gate insulator film; wherein the inter-poly silicon insulator film is constituted from a multilayer film including at least a tantalum pentoxide layer, and at least a part of the second MOS field effect transistors use the multilayer film including the tantalum pentoxide layer as gate insulator films.

Claim 49

A nonvolatile semiconductor memory device having an memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the floating gate through an inter-poly silicon insulator film, wherein the inter-poly silicon insulator film is constituted from a multilayer film including three layers comprising a first silicon dioxide layer formed over the floating gate, a layer having nitrogen and silicon as main constituent elements formed over the first silicon dioxide layer, and a tantalum pentoxide layer formed over the layer having nitrogen and silicon as the main constituent elements.

Claim 50

A nonvolatile semiconductor memory device having an memory array area constituted from a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells being a first MOS field effect transistor comprising a first well region formed in a semiconductor substrate, a first diffusion layer formed in the first well region, for functioning as a source or a drain, a floating gate formed over the first well region through a tunnel dielectric, and a control gate formed over the floating gate through an inter-poly silicon insulator film, wherein the inter-poly silicon insulator film is constituted from a multilayer film including three layers comprising a first silicon dioxide layer formed over the floating gate, a layer having nitrogen and silicon as main constituent elements formed over the first silicon dioxide layer, and a tantalum pentoxide layer formed over the layer having nitrogen and silicon as the main constituent elements.

Claim 51

The nonvolatile semiconductor memory device according to claim 37 , wherein the inter-poly silicon insulator film is constituted from a multilayer film including four layers comprising the first silicon dioxide layer formed over the floating gate, the layer having nitrogen and silicon as the main constituent elements formed over the first silicon dioxide layer, the tantalum pentoxide layer formed over the layer having nitrogen and silicon as the main constituent elements, and a second silicon dioxide layer formed over the tantalum pentoxide layer.

Claim 52

The nonvolatile semiconductor memory device according to claim 37 , wherein a density of a number of oxygen atoms included in the layer having nitrogen and silicon as the main constituent elements is smaller than a density of a number of nitrogen atoms therein.

Claim 53

The nonvolatile semiconductor memory device according to claim 37 , wherein the first silicon dioxide film has a thickness of 5 nm or less.

Claim 54

The nonvolatile semiconductor memory device according to claim 37 , wherein the layer having nitrogen and silicon as the main constituent elements has a thickness of 1.5 nm or more.

Claim 55

The nonvolatile semiconductor memory device according to claim 38 , wherein the second silicon dioxide film has a thickness of 2 nm or more.

Claim 56

The nonvolatile semiconductor memory device according to claim 37 , wherein the tantalum pentoxide layer has a dielectric constant of 50 or more.