US6207505B1
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Method for forming high density nonvolatile memories with high capacitive-coupling ratio
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1999-06-07
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Granted: 2001-03-27
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Expires: 2019-06-07
Abstract
Abstract A method for fabricating a high-speed and high-density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A thick thermal oxide is grown on the non-tunnel region. After removing the masking silicon nitride layer, the source and drain are formed by an ion implantation and a thermal annealing. The pad oxide film is then removed. A polysilicon film is deposited over the substrate 2 and then oxidized into sacrificial oxide layer. After stripping the sacrificial oxide layer, a rugged topography is then formed on the doped substrate regions. Thereafter, a thin oxide is grown on the rugged doped substrate region to form a rugged tunnel oxide. Finally, the floating gate, the interpoly dielectric, and the control gate are sequentially formed, and the memory cell is finished.
Inventors
- 👤 Shye-Lin Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 00:09
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10D64/01344; H10D64/01346; H10D64/031; H10D64/035; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/693
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
209 words
A method for forming a nonvolatile memory cell with rugged tunnel oxide layers, said method comprise: forming a silicon oxide layer on a semiconductor substrate; forming a silicon nitride layer on said silicon oxide layer; patterning said silicon nitride layer to define tunnel oxide region and expose a portion of said silicon oxide layer which defines a non-tunnel region of said semiconductor substrate; performing a first thermal oxidation to oxidize a portion of said semiconductor substrate exposed by said silicon nitride, thereby generating a non-tunnel oxide on said semiconductor substrate; removing said silicon nitride layer; implanting ions into said semiconductor substrate to form doped regions to serve as source and drain using said non-tunnel oxide as a mask; performing an annealing to said semiconductor substrate and simultaneously driving said ions into said semiconductor substrate; removing said silicon oxide layer; forming a polysilicon layer on said semiconductor substrate; performing a second thermal oxidation to convert said polysilicon layer into a sacrificial oxide layer; removing said sacrificial oxide layer; forming a dielectric layer on said doped regions to serve as said rugged tunnel oxides; forming a floating gate over said tunnel and non-tunnel oxides; forming a dielectric layer on said floating gate; and forming a control gate on said dielectric layer.
Claim 2
Independent Claim
209 words
A method for forming a nonvolatile memory cell with rugged tunnel oxide layers, said method comprise: forming a silicon oxide layer on a semiconductor substrate; forming a silicon nitride layer on said silicon oxide layer; patterning said silicon nitride layer to define tunnel oxide region and expose a portion of said silicon oxide layer which defines a non-tunnel region of said semiconductor substrate; performing a first thermal oxidation to oxidize a portion of said semiconductor substrate exposed by said silicon nitride, thereby generating a non-tunnel oxide on said semiconductor substrate; removing said silicon nitride layer; implanting ions into said semiconductor substrate to form doped regions to serve as source and drain using said non-tunnel oxide as a mask; performing an annealing to said semiconductor substrate and simultaneously driving said ions into said semiconductor substrate; removing said silicon oxide layer; forming a polysilicon layer on said semiconductor substrate; performing a second thermal oxidation to convert said polysilicon layer into a sacrificial oxide layer; removing said sacrificial oxide layer; forming a dielectric layer on said doped regions to serve as said rugged tunnel oxides; forming a floating gate over said tunnel and non-tunnel oxides; forming a dielectric layer on said floating gate; and forming a control gate on said dielectric layer.
Claim 3
Dependent Claim
14 words
the method according to claim 1 wherein said semiconductor substrate is a p-type substrate.
Claim 4
Dependent Claim
19 words
The method according to claim 1 , wherein said silicon oxide layer has a thickness of about 40-300 angstroms.
Claim 5
Dependent Claim
26 words
The method according to claim 1 , wherein said first thermal oxidation is performed in an oxygen steam ambience at a temperature of about 800-1100° C.
Claim 6
Dependent Claim
18 words
The method according to claim 1 , wherein said non-tunnel oxide has a thickness of about 300-2500 angstroms.
Claim 7
Dependent Claim
15 words
The method according to claim 1 , wherein said implanted impurity ions are n-type ions.
Claim 8
Dependent Claim
25 words
The method according to claim 6 , wherein said n-type ions are selected from the group consisting of phosphoric ions, arsenic ions and antimony ions.
Claim 9
Dependent Claim
28 words
The method according to claim 6 , wherein said n-type ions are implanted at about 0.5-150 keV with dosage of about 5×10 14 −5×10 16 atoms/cm 2 .
Claim 10
Dependent Claim
19 words
The method according to claim 1 , wherein said annealing is performed at a temperature of about 800-1150° C.
Claim 11
Dependent Claim
18 words
The method according to claim 1 , wherein said polysilicon layer has a thickness of about 20-300 angstroms.
Claim 12
Dependent Claim
27 words
The method according to claim 1 , wherein said polysilicon layer is formed by low pressure chemical vapor deposition (LPCVD) at a temperature of about 560-800° C.
Claim 13
Dependent Claim
26 words
The method according to claim 1 , wherein said second thermal oxidation is performed in a dry oxygen ambience at a temperature of about 800-1150° C.
Claim 14
Dependent Claim
44 words
The method according to claim 1 , wherein said sacrificial oxide layer is removed by a dry etching using a plasma source selected from the group consisting of CF 4 , CHF 3 , C 2 F 6 and C 3 F 8 .
Claim 15
Dependent Claim
39 words
The method according to claim 1 , wherein said sacrificial oxide layer is removed by a wet etching using a plasma source selected from the group consisting of buffered oxide-etching (BOE) solution and diluted solution of hydrofluoric acid (HF).
Claim 16
Dependent Claim
19 words
The method according to claim 1 , wherein said rugged tunnel oxide is formed by a third thermal oxidation.
Claim 17
Dependent Claim
26 words
The method according to claim 15 , wherein said third thermal oxidation is performed in a dry oxygen ambience at a temperature of about 750-1050° C.
Claim 18
Dependent Claim
19 words
The method according to claim 1 , wherein said rugged tunnel oxide is formed by a chemical vapor deposition.
Claim 19
Dependent Claim
21 words
The method according to claim 1 , wherein said rugged tunnel oxide is formed by a nitridation followed by a re-oxidation.
Claim 20
Dependent Claim
20 words
The method according to claim 1 , wherein said floating gate and said control gate are formed of doped polysilicon.
Claim 21
Dependent Claim
55 words
The method according to claim 1 , wherein said dielectric layer is formed of a material selected from the group consisting of tantalum pentoxide (Ta 2 O 5 ), barium strontium titanate (BST), a double film of silicon nitride and silicon oxide, and a triple film of silicon oxide, silicon nitride and silicon oxide (ONO).
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