US6008091A
Expired / Lapsed
US
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Floating gate avalanche injection MOS transistors with high K dielectric control gates
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1998-01-27
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Granted: 1999-12-28
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Expires: 2018-01-27
Abstract
Abstract The specification describes intergate dielectrics between the floating silicon gate and the control silicon gate in MOS memory devices. The intergate dielectrics are composite structures of SiO 2 --Ta 2 O 5 --SiO 2 with the first SiO 2 layer grown on the floating gate,, and all layers preferably produced in situ in an LPCVD reactor. After formation of the composite SiO 2 --Ta 2 O 5 --SiO 2 dielectric, it is annealed at low pressure to densify the SiO 2 layers. Electrical measurements show that the charge trap density in the intergate dielectric is substantially lower than in layered dielectrics produced by prior techniques.
Inventors
- 👤 Richard William Gregor
- 👤 Isik C. Kizilyalli
- 👤 Pradip Kumar Roy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:24
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10P; H10P10/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
196 words
Method for the manufacture of a MOS silicon device comprising the steps of: a. forming a first dielectric layer on a silicon substrate, b. forming a silicon floating gate on the first dielectric layer, c. forming a second dielectric layer on the silicon floating gate, and d. forming a silicon control gate on the second dielectric layer, the invention characterized in the second dielectric layer is a composite layer of SiO 2 --Ta 2 O 5 --SiO 2 formed by the steps of: i. growing a first SiO 2 layer on the silicon floating gate, said first SiO 2 layer having a thickness in the range 10-30 Angstroms, ii. depositing a layer of Ta 2 O 5 on the first SiO 2 layer, said layer of Ta 2 O 5 having a thickness in the range 30-100 Angstroms, and iii. depositing a second layer of SiO 2 over said layer of Ta 2 O 5 said second layer of SiO 2 having a thickness in the range 5-30 Angstroms, the invention further characterized in that the overall thickness of the SiO 2 --Ta 2 O 5 --SiO 2 composite layer is in the range 45-100 Angstroms.
Claim 2
Dependent Claim
196 words
Method for the manufacture of a MOS silicon device comprising the steps of: a. forming a first dielectric layer on a silicon substrate, b. forming a silicon floating gate on the first dielectric layer, c. forming a second dielectric layer on the silicon floating gate, and d. forming a silicon control gate on the second dielectric layer, the invention characterized in the second dielectric layer is a composite layer of SiO 2 --Ta 2 O 5 --SiO 2 formed by the steps of: i. growing a first SiO 2 layer on the silicon floating gate, said first SiO 2 layer having a thickness in the range 10-30 Angstroms, ii. depositing a layer of Ta 2 O 5 on the first SiO 2 layer, said layer of Ta 2 O 5 having a thickness in the range 30-100 Angstroms, and iii. depositing a second layer of SiO 2 over said layer of Ta 2 O 5 said second layer of SiO 2 having a thickness in the range 5-30 Angstroms, the invention further characterized in that the overall thickness of the SiO 2 --Ta 2 O 5 --SiO 2 composite layer is in the range 45-100 Angstroms.
Claim 3
Dependent Claim
30 words
The method of claim 1 further including the step of annealing the SiO 2 --Ta 2 O 5 --SiO 2 composite layer at a temperature in the range 550-750° C.
Claim 4
Dependent Claim
24 words
The method of claim 2 wherein the steps i-iii are carried out in a LPCVD reactor and each step is carried out in situ.
Claim 5
Dependent Claim
17 words
The method of claim 3 wherein the silicon control floating gate and the silicon gate are polysilicon.
Claim 6
Dependent Claim
14 words
The method of claim 4 wherein the first dielectric layer is SiO 2 .
Claim 7
Dependent Claim
384 words
Method for the manufacture of an MOS silicon device comprising the steps of: a. forming a first dielectric layer on a silicon substrate, b. forming a silicon floating gate on the first dielectric layer, c. forming a second dielectric layer on the silicon floating gate, and d. forming a silicon control gate on the second dielectric layer, the invention characterized in the second dielectric layer is a composite layer of SiO 2 --Ta 2 O 5 --SiO 2 formed by the steps of: i. placing the silicon substrate in a LPCVD reactor, ii. heating the silicon substrate to a temperature in the range 700-950° C., iii. growing a first SiO 2 layer on the silicon floating gate in an atmosphere comprising oxygen at a pressure in the range 0.7-1.0 Torr to produce a SiO 2 layer having a thickness in the range 10-30 Angstroms, iv. adjusting the temperature of said silicon substrate to a temperature in the range 300-500° C., v. adjusting the pressure in said LPCVD reactor to a pressure in the range 50-200 mTorr, vi. introducing precursor gases into said LPCVD reactor to deposit a layer of Ta 2 O 5 on the first SiO 2 layer, said layer of Ta 2 O 5 having a thickness in the range 30-100 Angstroms, vii. adjusting the temperature of said silicon substrate to a temperature in the range 500-750° C., viii. adjusting the pressure in said LPCVD reactor to a pressure in the range 150-350° C., ix. introducing an oxide precursor gas into said LPCVD reactor and depositing a second layer of SiO 2 over said layer of Ta 2 O 5 , said second layer of SiO 2 having a thickness in the range 5-30 Angstroms, thereby forming a composite layer of SiO 2 --Ta 2 O 5 --SiO 2 , x. adjusting the temperature of said silicon substrate to a temperature in the range 550-750° C., xi. adjusting the pressure in said LPCVD reactor to a pressure in the range 0.7-1.1 Torr, and xii. annealing the composite layer of SiO 2 --Ta 2 O 5 --SiO 2 for a period of 15 to 100 min, the invention further characterized in that the overall thickness of the SiO 2 --Ta 2 O 5 --SiO 2 composite layer is in the range 45-100 Angstroms.
Claim 8
Dependent Claim
384 words
Method for the manufacture of an MOS silicon device comprising the steps of: a. forming a first dielectric layer on a silicon substrate, b. forming a silicon floating gate on the first dielectric layer, c. forming a second dielectric layer on the silicon floating gate, and d. forming a silicon control gate on the second dielectric layer, the invention characterized in the second dielectric layer is a composite layer of SiO 2 --Ta 2 O 5 --SiO 2 formed by the steps of: i. placing the silicon substrate in a LPCVD reactor, ii. heating the silicon substrate to a temperature in the range 700-950° C., iii. growing a first SiO 2 layer on the silicon floating gate in an atmosphere comprising oxygen at a pressure in the range 0.7-1.0 Torr to produce a SiO 2 layer having a thickness in the range 10-30 Angstroms, iv. adjusting the temperature of said silicon substrate to a temperature in the range 300-500° C., v. adjusting the pressure in said LPCVD reactor to a pressure in the range 50-200 mTorr, vi. introducing precursor gases into said LPCVD reactor to deposit a layer of Ta 2 O 5 on the first SiO 2 layer, said layer of Ta 2 O 5 having a thickness in the range 30-100 Angstroms, vii. adjusting the temperature of said silicon substrate to a temperature in the range 500-750° C., viii. adjusting the pressure in said LPCVD reactor to a pressure in the range 150-350° C., ix. introducing an oxide precursor gas into said LPCVD reactor and depositing a second layer of SiO 2 over said layer of Ta 2 O 5 , said second layer of SiO 2 having a thickness in the range 5-30 Angstroms, thereby forming a composite layer of SiO 2 --Ta 2 O 5 --SiO 2 , x. adjusting the temperature of said silicon substrate to a temperature in the range 550-750° C., xi. adjusting the pressure in said LPCVD reactor to a pressure in the range 0.7-1.1 Torr, and xii. annealing the composite layer of SiO 2 --Ta 2 O 5 --SiO 2 for a period of 15 to 100 min, the invention further characterized in that the overall thickness of the SiO 2 --Ta 2 O 5 --SiO 2 composite layer is in the range 45-100 Angstroms.
Claim 9
Dependent Claim
28 words
The method of claim 6 wherein the atmosphere in said LPCVD reactor during step xii. is selected from the group consisting of O 2 and N 2 .
Claim 10
Dependent Claim
96 words
The method of claim 6 in which the temperature in step ii. is in the range 800-900° C., the pressure in step iii is in the range 0.8-0.9 Torr, the temperature in step iv. is in the range 375-430° C., the pressure in step v. is in the range 75-150 mTorr, the temperature in step vii. is in the range 600-700° C., the pressure in step viii. is in the range 200-300 mTorr, the temperature in step x. is in the range 600-700° C., and the pressure in step xi. is in the range 0.8-1.0 Torr.
Claim 11
Dependent Claim
12 words
The method of claim 6 wherein steps iv. through ix. are repeated.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-12-27 | 2003-06-28 | 2003-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-27 | 2007-06-28 | 2007-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-27 | 2011-06-28 | 2011-12-28 | $7700.00 | Window Closed / Lapsed |