US4943836A
Expired / Lapsed
US
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Ultraviolet erasable nonvolatile semiconductor device
Assignee: Toshiba Corp
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Filing: 1988-07-25
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Granted: 1990-07-24
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Expires: 2008-07-25
Abstract
Abstract An ultraviolet erasable nonvolatile seimconductor device has a floating gate, a conrol gate, and a gate insulating layer interlayered between the floating gate and the control gate. The interlayered gate insulating layer consists of three layers, a first silicon oxide layer, a silicon nitride layer layered on the first silicon oxide layer, and a second silicon oxide layer. The second silicon oxide layer as the top layer of the three-layered gate insulating layer is 30 Å or less in thickness.
Inventors
- 👤 Seiichi Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:33
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
120 words
An ultraviolet erasable nonvolatile semiconductor device comprising: a first conductivity-type semiconductor substrate; source and drain regions formed in a surface of said substrate; a first gate insulating layer consisting of a single silicon oxide layer formed on a portion of said surface between said source and drain regions; a floating gate provided on said silicon oxide layer; a second gate insulating layer formed on said floating gate, said second gate insulating layer consisting of a first silicon oxide layer, a silicon nitride layer formed on said first silicon oxide layer, and a second silicon oxide layer having a thickness of 30 Å or less formed on said silicon nitride layer; and a control gate provided on said gate insulating layer.
Claim 2
Dependent Claim
120 words
An ultraviolet erasable nonvolatile semiconductor device comprising: a first conductivity-type semiconductor substrate; source and drain regions formed in a surface of said substrate; a first gate insulating layer consisting of a single silicon oxide layer formed on a portion of said surface between said source and drain regions; a floating gate provided on said silicon oxide layer; a second gate insulating layer formed on said floating gate, said second gate insulating layer consisting of a first silicon oxide layer, a silicon nitride layer formed on said first silicon oxide layer, and a second silicon oxide layer having a thickness of 30 Å or less formed on said silicon nitride layer; and a control gate provided on said gate insulating layer.
Claim 3
Dependent Claim
21 words
The semiconductor device according to claim 1, wherein the thickness of said second silicon oxide layer is 20 Å or less.
Claim 4
Dependent Claim
39 words
The semiconductor device according to claim 1, wherein when said first silicon oxide layer and said silicon nitride layer are each 100 to 200 Å in thickness, and said second silicon layer is 10 Å or more in thickness.
References Cited (Backward Citations)
US4495693A
Cited
FR2533740A1
Cited
US4630086A
Cited
US4577390A
Cited
EP0187278A2
Cited
US4665426A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-23 | 1994-01-22 | 1994-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-23 | 1998-01-22 | 1998-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-23 | 2002-01-22 | 2002-07-24 | $7700.00 | Window Closed / Lapsed |