US4613956A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Floating gate memory with improved dielectric
Assignee: Texas Instruments Inc
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Filing: 1983-02-23
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Granted: 1986-09-23
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Expires: 2003-02-23
Abstract
Abstract The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide tight coupling of the control to the floating gate, but also provides excellent dielectric integrity. Moreover, the thickness of this dielectric layer does not exhibit any uncontrolled increase during exposure to second gate oxidation. Thus, the polysilicon-to-polysilicon dielectric is not only of high specific capacitance and high integrity, it is also very uniform.
Inventors
- 👤 James L. Paterson
- 👤 Roger A. Haken
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:30
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/43; H10B41/47; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01346
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
133 words
A floating gate memory cell, comprising: (a) a silicon substrate; (b) a plurality of polysilicon insulated floating gates on said silicon substrate, said floating gates defining respective channel regions beneath said respective floating gates in the surface of said substrate; (c) a plurality of polysilicon control gates over respective ones of said floating gates; (d) a composite dielectric comprising both silicon nitride and silicon dioxide disposed between said control gates and said respective floating gates; (e) a plurality of source and drain regions respectively separated by respective ones of said channel regions; and (f) means for applying a write voltage to a selected one of said control gates, (g) said voltage being about 15 volts when said dielectric is about 400 angstroms, said voltage varying therefrom proportionally with the thickness of said dielectric.
Claim 2
Dependent Claim
133 words
A floating gate memory cell, comprising: (a) a silicon substrate; (b) a plurality of polysilicon insulated floating gates on said silicon substrate, said floating gates defining respective channel regions beneath said respective floating gates in the surface of said substrate; (c) a plurality of polysilicon control gates over respective ones of said floating gates; (d) a composite dielectric comprising both silicon nitride and silicon dioxide disposed between said control gates and said respective floating gates; (e) a plurality of source and drain regions respectively separated by respective ones of said channel regions; and (f) means for applying a write voltage to a selected one of said control gates, (g) said voltage being about 15 volts when said dielectric is about 400 angstroms, said voltage varying therefrom proportionally with the thickness of said dielectric.
Claim 3
Dependent Claim
25 words
The device of claim 1 further comprising means for applying a read voltage between a selected one of said sources and said respective corresponding drain.
Claim 4
Dependent Claim
134 words
A floating gate memory cell, comprising: (a) a silicon substrate; (b) a plurality of polysilicon insulated floating gates on said silicon substrate, said floating gates defining respective channel regions beneath said respective floating gates in the surface of said substrate; (c) a plurality of polysilicon control gates over respective ones of said floating gates; (d) a composite dielectric comprising both silicon nitride and silicon dioxide disposed between said control gates and said respective floating gates ; (e) a plurality of source and drain regions respectively separated by respective ones of said channel regions; and (f) means for applying a write voltage to a selected one of said control gates, (g) said voltage being about 21 volts when said dielectric is about 600 angstroms, said voltage varying therefrom proportionally with the thickness of said dielectric.
Claim 5
Dependent Claim
134 words
A floating gate memory cell, comprising: (a) a silicon substrate; (b) a plurality of polysilicon insulated floating gates on said silicon substrate, said floating gates defining respective channel regions beneath said respective floating gates in the surface of said substrate; (c) a plurality of polysilicon control gates over respective ones of said floating gates; (d) a composite dielectric comprising both silicon nitride and silicon dioxide disposed between said control gates and said respective floating gates ; (e) a plurality of source and drain regions respectively separated by respective ones of said channel regions; and (f) means for applying a write voltage to a selected one of said control gates, (g) said voltage being about 21 volts when said dielectric is about 600 angstroms, said voltage varying therefrom proportionally with the thickness of said dielectric.
Claim 6
Dependent Claim
25 words
The device of claim 3 further comprising means for applying a read voltage between a selected one of said sources and said respective corresponding drain.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-22 | 1990-03-24 | 1990-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-22 | 1994-03-24 | 1994-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-22 | 1998-03-24 | 1998-09-23 | $7700.00 | Window Closed / Lapsed |