Patent US7031183B2 successfully refreshed from Google Patents.
US7031183B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
MRAM device integrated with other types of circuitry
Assignee: Everspin Technologies Inc
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Filing: 2003-12-08
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Granted: 2006-04-18
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Expires: 2023-12-08
Abstract
Abstract A magnetoresistive random access memory (MRAM) is embedded with another circuit type. Logic, such as a processing unit, is particularly well-suited circuit type for embedding with MRAM. The embedding is made more efficient by using a metal layer that is used as part of the interconnect for the other circuit also as part of the MRAM cell. The MRAM cells are all written by program lines, which are the two lines that cross to define a cell to be written. Thus, the design is simplified because there is commonality of usage of the metal line that is used for one of the program lines for the MRAM and for one of the interconnect lines for the logic.
Inventors
- 👤 Gloria J. Kerszykowski
- 👤 Li Hsin Chang
- 👤 Mark A. Durlam
- 👤 Mitchell T. Lien
- 👤 Thomas V. Meixner
- 👤 Loren J. Wise
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:20
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/02; G11C11/14; G11C11/15
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
188 words
A semiconductor device, comprising: a semiconductor substrate having a first portion for an MRAM and a second portion for a first circuit type, wherein the first circuit type is different than MRAM; first front end circuitry for the MRAM over the first portion in the substrate; second front end circuitry for the first circuit type in the second portion of the substrate; an MRAM cell over the first front end circuitry, wherein the MRAM cell uses a first metal layer for a first program line; a metal interconnect over the second front end circuitry, wherein the metal interconnect uses the first metal layer to provide interconnect for the first circuit type; and a third metal layer over the first and second metal layers and a fourth metal layer over the third metal layer, wherein the third and fourth metal layers are both thicker than the first and second metal layers; wherein the MRAM cell is characterized as using a second metal layer for a second program line and the metal interconnect is characterized as using the second metal layer to provide interconnect for the first type of circuitry.
Claim 2
Dependent Claim
188 words
A semiconductor device, comprising: a semiconductor substrate having a first portion for an MRAM and a second portion for a first circuit type, wherein the first circuit type is different than MRAM; first front end circuitry for the MRAM over the first portion in the substrate; second front end circuitry for the first circuit type in the second portion of the substrate; an MRAM cell over the first front end circuitry, wherein the MRAM cell uses a first metal layer for a first program line; a metal interconnect over the second front end circuitry, wherein the metal interconnect uses the first metal layer to provide interconnect for the first circuit type; and a third metal layer over the first and second metal layers and a fourth metal layer over the third metal layer, wherein the third and fourth metal layers are both thicker than the first and second metal layers; wherein the MRAM cell is characterized as using a second metal layer for a second program line and the metal interconnect is characterized as using the second metal layer to provide interconnect for the first type of circuitry.
Claim 3
Dependent Claim
19 words
The semiconductor device of claim 1 , wherein the third and fourth metal layers have substantially the same thickness.
Claim 4
Dependent Claim
20 words
The semiconductor device of claim 2 , wherein a portion of the first metal layer functions as a digit line.
Claim 5
Dependent Claim
20 words
The semiconductor device of claim 3 , wherein a portion of the second metal line functions as a bit line.
Claim 6
Dependent Claim
41 words
The semiconductor device of claim 2 , wherein the third and fourth layers are separated by a first distance and the second and third layers are separated by a second distance, wherein the second distance is greater than the first distance.
Claim 7
Dependent Claim
42 words
The semiconductor device of claim 2 , wherein the third and fourth layers are separated by a first distance and the second and third layers are separated by a second distance, wherein the second distance is substantially equal to the first distance.
Claim 8
Dependent Claim
17 words
The semiconductor device of claim 1 , wherein the fourth layer is thicker than the third layer.
Claim 9
Dependent Claim
42 words
The semiconductor device of claim 7 , wherein the third and fourth metal layers are connected by vias of a first width and the third and second metal layers are connected by vias of a second width greater than the first width.
Claim 10
Dependent Claim
170 words
A semiconductor device, comprising: a semiconductor substrate having a first portion for an MRAM and a second portion for a first circuit type, wherein the first circuit type is different than MRAM; first front end circuitry for the MRAM over the first portion in the substrate; second front end circuitry for the first circuit type in the second portion of the substrate; an MRAM cell over the first front end circuitry, wherein the MRAM cell uses a first metal layer for a first program line; a metal interconnect over the second front end circuitry, wherein the metal interconnect uses the first metal layer to provide interconnect for the first circuit type; and a third metal layer having a first portion over the first portion of the substrate and a second portion over the second portion of the substrate, wherein the first portion of the third metal layer is immediately over the second metal layer and the second portion of the third metal layer is immediately over the second metal layer.
Claim 11
Dependent Claim
170 words
A semiconductor device, comprising: a semiconductor substrate having a first portion for an MRAM and a second portion for a first circuit type, wherein the first circuit type is different than MRAM; first front end circuitry for the MRAM over the first portion in the substrate; second front end circuitry for the first circuit type in the second portion of the substrate; an MRAM cell over the first front end circuitry, wherein the MRAM cell uses a first metal layer for a first program line; a metal interconnect over the second front end circuitry, wherein the metal interconnect uses the first metal layer to provide interconnect for the first circuit type; and a third metal layer having a first portion over the first portion of the substrate and a second portion over the second portion of the substrate, wherein the first portion of the third metal layer is immediately over the second metal layer and the second portion of the third metal layer is immediately over the second metal layer.
Claim 12
Dependent Claim
170 words
A semiconductor device, comprising: a semiconductor substrate having a first portion for an MRAM and a second portion for a first circuit type, wherein the first circuit type is different than MRAM; first front end circuitry for the MRAM over the first portion in the substrate; second front end circuitry for the first circuit type in the second portion of the substrate; an MRAM cell over the first front end circuitry, wherein the MRAM cell uses a first metal layer for a first program line; a metal interconnect over the second front end circuitry, wherein the metal interconnect uses the first metal layer to provide interconnect for the first circuit type; and a third metal over the second metal layer, wherein the third metal layer has a first portion over the first portion of the substrate and a second portion over the second portion of the substrate, wherein the second portion is substantially coterminous with the second layer and is connected to the second layer by a plurality of vias.
Claim 13
Dependent Claim
170 words
A semiconductor device, comprising: a semiconductor substrate having a first portion for an MRAM and a second portion for a first circuit type, wherein the first circuit type is different than MRAM; first front end circuitry for the MRAM over the first portion in the substrate; second front end circuitry for the first circuit type in the second portion of the substrate; an MRAM cell over the first front end circuitry, wherein the MRAM cell uses a first metal layer for a first program line; a metal interconnect over the second front end circuitry, wherein the metal interconnect uses the first metal layer to provide interconnect for the first circuit type; and a third metal over the second metal layer, wherein the third metal layer has a first portion over the first portion of the substrate and a second portion over the second portion of the substrate, wherein the second portion is substantially coterminous with the second layer and is connected to the second layer by a plurality of vias.
Claim 14
Dependent Claim
21 words
The semiconductor device of claim 10 , wherein the MRAM cell uses the second metal layer for a second program line.
Claim 15
Dependent Claim
239 words
A semiconductor device, comprising: a semiconductor substrate having a first portion for an MRAM and a second portion for a circuit of a type different than MRAM; a first metal layer having a first portion over the first portion of the substrate and a second portion over the second portion of the substrate, wherein the first portion of the first metal layer is used as a first program line for the MRAM and the second portion of the first metal line is used for interconnecting the circuit; a second metal layer over the first metal layer having a first portion over the first portion of the substrate and a second portion over the seconds portion of the substrate, wherein the first portion of the second metal layer is used for a second program line of the MRAM and the second portion of the second metal layer is used for interconnecting the circuit; and a third metal layer having a first portion over the first portion of the substrate and a second portion over the second portion of the substrate, wherein the second portion of the third metal layer is connected to the second portion of the second layer by a first via having a first length; and the second portion of the second metal layer is connected to the second portion of the first metal layer by a second via having a second length greater than the first length.
Claim 16
Dependent Claim
239 words
A semiconductor device, comprising: a semiconductor substrate having a first portion for an MRAM and a second portion for a circuit of a type different than MRAM; a first metal layer having a first portion over the first portion of the substrate and a second portion over the second portion of the substrate, wherein the first portion of the first metal layer is used as a first program line for the MRAM and the second portion of the first metal line is used for interconnecting the circuit; a second metal layer over the first metal layer having a first portion over the first portion of the substrate and a second portion over the seconds portion of the substrate, wherein the first portion of the second metal layer is used for a second program line of the MRAM and the second portion of the second metal layer is used for interconnecting the circuit; and a third metal layer having a first portion over the first portion of the substrate and a second portion over the second portion of the substrate, wherein the second portion of the third metal layer is connected to the second portion of the second layer by a first via having a first length; and the second portion of the second metal layer is connected to the second portion of the first metal layer by a second via having a second length greater than the first length.
Claim 17
Dependent Claim
21 words
The semiconductor device of claim 12 , wherein the third metal layer is the last metal layer of the semiconductor device.
Claim 18
Dependent Claim
21 words
The semiconductor device of claim 12 , wherein the second portions of the second and third metal layers are substantially coterminous.
Claim 19
Dependent Claim
40 words
The semiconductor device of claim 12 , further comprising a fourth metal layer over the third metal layer having a first portion over the first portion of the substrate and a second portion over the second portion of the substrate.
Claim 20
Dependent Claim
23 words
The semiconductor device of claim 15 , wherein the fourth metal layer has a thickness greater than that of the third metal layer.
Claim 21
Dependent Claim
22 words
The semiconductor device of claim 15 , wherein the fourth metal layer is connected to the third metal layer by a via.
Claim 22
Dependent Claim
171 words
A semiconductor device, comprising: a semiconductor substrate having a first portion for an MRAM and a second portion for a circuit of a type different than MRAM; a first metal layer having a first portion over the first portion of the substrate and a second portion over the second portion of the substrate, wherein the first portion of the first metal layer is used as a first program line for the MRAM and the second portion of the first metal line is used for interconnecting the circuit; a second metal layer over the first metal layer over the first portion of the substrate used for a second program line of the MRAM; and a third metal layer having a first portion over the first portion of the substrate and a second portion over the second portion of the substrate, wherein the first portion of the third metal layer is immediately over the second metal layer and the second portion of the third metal layer is immediately over the first metal layer.
Claim 23
Dependent Claim
171 words
A semiconductor device, comprising: a semiconductor substrate having a first portion for an MRAM and a second portion for a circuit of a type different than MRAM; a first metal layer having a first portion over the first portion of the substrate and a second portion over the second portion of the substrate, wherein the first portion of the first metal layer is used as a first program line for the MRAM and the second portion of the first metal line is used for interconnecting the circuit; a second metal layer over the first metal layer over the first portion of the substrate used for a second program line of the MRAM; and a third metal layer having a first portion over the first portion of the substrate and a second portion over the second portion of the substrate, wherein the first portion of the third metal layer is immediately over the second metal layer and the second portion of the third metal layer is immediately over the first metal layer.
Claim 24
Dependent Claim
71 words
The semiconductor device of claim 18 , further comprising: a first via connecting the first portion of the second metal layer to the first portion of the first metal layer, the first via having a first length; and a second via connecting the second portion of the third metal layer to the second portion of the first metal layer, the second via having a second length greater than the first length.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-04-17 | 2009-10-17 | 2010-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-04-17 | 2013-10-17 | 2014-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-04-17 | 2017-10-17 | 2018-04-18 | $7700.00 | Window Closed / Lapsed |