US5940319A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Magnetic random access memory and fabricating method thereof
Assignee: Everspin Technologies Inc
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Filing: 1998-08-31
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Granted: 1999-08-17
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Expires: 2018-08-31
Abstract
Abstract An improved and novel MRAM device with magnetic memory elements and circuitry for controlling magnetic memory elements is provided. The circuitry, for example, transistor (12a) having a gate (17a), a drain (18) and a source (16a) is integrated on a substrate (11) and coupled to a magnetic memory element (43) on the circuitry through a plug conductor (19a) and a conductor line (45). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (43, 44). Digit line (29) and bit line (48) are placed under and on top of magnetic memory element (43), respectively, and enabled to access magnetic memory element (43). These lines are enclosed by a high permeability layer (31, 56, 58) excluding a surface facing magnetic memory element (43), which shields and focuses a magnetic field toward magnetic memory element (43).
Inventors
- 👤 Mark Durlam
- 👤 Gloria Kerszykowski
- 👤 Jon Slaughter
- 👤 Theodore Zhu
- 👤 Eugene Chen
- 👤 Saied N. Tehrani
- 👤 Kelly W. Kyler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 00:56
CPC Classifications
B; B82; B82Y; B82Y10/00; G; G11; G11C; G11C11/00; G11C11/02; G11C11/14; G11C11/15; H; H10; H10B; H10B61/00; H10B61/10; H10B61/20; H10B61/22
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
178 words
A random access memory having a magnetic memory cell and circuitry for controlling operations of the magnetic memory cell comprising: a substrate on which the magnetic memory cell and the circuitry are formed; the circuitry comprising: a current control element, being electrically coupled to the magnetic memory cell, for controlling a sense current supplied to the magnetic memory cell, and a first electrically conductive line being electrically isolated from the magnetic memory cell, and generating a magnetic field at the magnetic memory cell when a current is provided in the first electrically conductive line; a field focusing layer enclosing the first electrically conductive line excluding a portion facing the magnetic memory cell, which facilitates a magnetic field generated by the current in the first electrically conductive line to concentrate on the magnetic memory cell; the magnetic memory cell on the circuitry having magnetic layers separated by a non-magnetic layer; and a second electrically conductive line on the magnetic memory cell being electrically coupled to the magnetic memory cell and being perpendicularly placed to the first electrically conductive line.
Claim 2
Dependent Claim
178 words
A random access memory having a magnetic memory cell and circuitry for controlling operations of the magnetic memory cell comprising: a substrate on which the magnetic memory cell and the circuitry are formed; the circuitry comprising: a current control element, being electrically coupled to the magnetic memory cell, for controlling a sense current supplied to the magnetic memory cell, and a first electrically conductive line being electrically isolated from the magnetic memory cell, and generating a magnetic field at the magnetic memory cell when a current is provided in the first electrically conductive line; a field focusing layer enclosing the first electrically conductive line excluding a portion facing the magnetic memory cell, which facilitates a magnetic field generated by the current in the first electrically conductive line to concentrate on the magnetic memory cell; the magnetic memory cell on the circuitry having magnetic layers separated by a non-magnetic layer; and a second electrically conductive line on the magnetic memory cell being electrically coupled to the magnetic memory cell and being perpendicularly placed to the first electrically conductive line.
Claim 3
Dependent Claim
22 words
The random access memory as claimed in claim 1 wherein the circuitry is fabricated by a complimentary metal oxide semiconductor (CMOS) process.
Claim 4
Dependent Claim
33 words
The random access memory as claimed in claim 1 further including a field focusing layer overlying the second electrically conductive line which facilitates a magnetic field to concentrate on the magnetic memory cell.
Claim 5
Dependent Claim
17 words
The random access memory as claimed in claim 1 wherein the current control element is a transistor.
Claim 6
Dependent Claim
22 words
The random access memory as claimed in claim 1 wherein the magnetic memory cell forms a tunneling junction between the magnetic layers.
Claim 7
Dependent Claim
177 words
A random access memory having a magnetic memory cell and circuitry for controlling operations of the magnetic memory cell comprising: a substrate on which the magnetic memory cell and the circuitry are formed; the circuitry comprising: a current control element, being electrically coupled to the magnetic memory cell, for controlling a sense current supplied to the magnetic memory cell, and a first electrically conductive line being electrically coupled to the current control element and enclosed by a field focusing layer which facilitates a magnetic field generated by the current in the first electrically conductive line to concentrate on the magnetic memory cell, excluding a portion facing toward the magnetic memory cell; the magnetic memory cell on the circuitry having magnetic layers separated by a non-magnetic layer; a second electrically conductive line on the magnetic memory cell being electrically coupled to the magnetic memory cell and being perpendicularly placed to the first electrically conductive line; and a field focusing layer overlying the second electrically conductive line which facilitates a magnetic field to concentrate to the magnetic memory cell.
Claim 8
Dependent Claim
177 words
A random access memory having a magnetic memory cell and circuitry for controlling operations of the magnetic memory cell comprising: a substrate on which the magnetic memory cell and the circuitry are formed; the circuitry comprising: a current control element, being electrically coupled to the magnetic memory cell, for controlling a sense current supplied to the magnetic memory cell, and a first electrically conductive line being electrically coupled to the current control element and enclosed by a field focusing layer which facilitates a magnetic field generated by the current in the first electrically conductive line to concentrate on the magnetic memory cell, excluding a portion facing toward the magnetic memory cell; the magnetic memory cell on the circuitry having magnetic layers separated by a non-magnetic layer; a second electrically conductive line on the magnetic memory cell being electrically coupled to the magnetic memory cell and being perpendicularly placed to the first electrically conductive line; and a field focusing layer overlying the second electrically conductive line which facilitates a magnetic field to concentrate to the magnetic memory cell.
Claim 9
Dependent Claim
22 words
The random access memory as claimed in claim 6 wherein the circuitry is fabricated by a complimentary metal oxide semiconductor (CMOS) process.
Claim 10
Dependent Claim
17 words
The random access memory as claimed in claim 6 wherein the current control element is a diode.
Claim 11
Dependent Claim
177 words
A random access memory device having a plurality of magnetic memory units on a substrate, each magnetic memory unit including a magnetic memory cell and circuitry for controlling operations of the magnetic memory cell, the magnetic memory unit further comprising: the circuitry comprising: a current control element, being electrically coupled to the magnetic memory cell, for controlling a sense current supplied to the magnetic memory cell, and a first electrically conductive line being enclosed by a field focusing layer which facilitates a magnetic field generated by the current in the first electrically conductive line to concentrate on the magnetic memory cell, excluding a portion facing toward the magnetic memory cell; and the magnetic memory cell on the circuitry having magnetic layers separated by a non-magnetic layer; a second electrically conductive line on the magnetic memory cell being electrically coupled to the magnetic memory cell and being perpendicularly placed to the first electrically conductive line; and a field focusing layer overlying the second electrically conductive line which facilitates a magnetic field to concentrate on the magnetic memory cell.
Claim 12
Dependent Claim
177 words
A random access memory device having a plurality of magnetic memory units on a substrate, each magnetic memory unit including a magnetic memory cell and circuitry for controlling operations of the magnetic memory cell, the magnetic memory unit further comprising: the circuitry comprising: a current control element, being electrically coupled to the magnetic memory cell, for controlling a sense current supplied to the magnetic memory cell, and a first electrically conductive line being enclosed by a field focusing layer which facilitates a magnetic field generated by the current in the first electrically conductive line to concentrate on the magnetic memory cell, excluding a portion facing toward the magnetic memory cell; and the magnetic memory cell on the circuitry having magnetic layers separated by a non-magnetic layer; a second electrically conductive line on the magnetic memory cell being electrically coupled to the magnetic memory cell and being perpendicularly placed to the first electrically conductive line; and a field focusing layer overlying the second electrically conductive line which facilitates a magnetic field to concentrate on the magnetic memory cell.
Claim 13
Dependent Claim
23 words
The random access memory device as claimed in claim 9 wherein the circuitry is fabricated by a complimentary metal oxide semiconductor (CMOS) process.
Claim 14
Dependent Claim
22 words
The random access memory as claimed in claim 9 wherein the magnetic memory cell forms a tunneling junction between the magnetic layers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-16 | 2003-02-15 | 2003-08-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-16 | 2007-02-15 | 2007-08-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-16 | 2011-02-15 | 2011-08-17 | $7700.00 | Window Closed / Lapsed |