Ring-resister controlled DLL with fine delay line and direct skew sensing detector

Claim 2

A ring-register controlled delay locked loop comprising: a phase detecting means for comparing an internal clock signal with an output clock signal which is fed back from an output terminal of the ring-register controlled delay locked loop and producing a control signal in order to synchronize the internal clock signal with the output clock signal; a fine delay means for carrying out a fine delay of the internal clock signal in response to the control signal from the phase detecting means or for bypassing the control signal from the phase detecting means; a coarse delay means having a plurality of unit delayers which are coupled to each other in a ring type, for coarsely delaying the internal clock signal from the fine delay means in response to the bypassed control signal; an output clock signal generating means for the output clock signal when a desired delay is achieved in the coarse delay means; and a delay model for delaying the output clock signal and transferring the delayed output clock signal to the phase detecting means.

Claim 3

The ring-register controlled delay locked loop as recited in claim 1 , wherein the fine delay means includes: a fine delay line for delaying the internal clock signal by providing capacitive load to the internal clock signal, having a plurality of capacitors connected to a signal path of the internal clock signal; and a control means for selectively connecting the capacitors to the signal path of the internal clock signal in response to the control signal from the phase detecting means or for bypassing the control signal from the phase detecting means.

Claim 4

The ring-register controlled delay locked loop as recited in claim 2 , wherein the coarse delay means includes: a backward ring delay means having a plurality of delay stages, which are circularly connected to each other, for coarsely delaying the delayed internal clock signal by the fine delay means; and a register means for controlling an amount of delay of the internal clock signal from the fine delay means in the circularly connected delay stages in response to the bypassed control signal from the phase detecting means.

Claim 5

The ring-register controlled delay locked loop as recited in claim 3 , wherein each of the delay stages of the backward ring delay means includes: a first NAND gate receiving an output signal from the register means and the internal clock signal from the fine delay means; a second NAND gate receiving an output signal from the first NAND gate and an output signal from the circularly connected delay stage; and a third NAND gate receiving an output signal from the second NAND gate and a reset signal.

Claim 6

The ring-register controlled delay locked loop as recited in claim 3 , wherein the coarse delay means satisfies the following relationship: |τ FD −τ VAR,max |≦τ FD where τ CD is a delay time in the delay stage of the coarse delay means, τ VAR,max is a maximum delay time in the fine delay means, and τ CD is a delay time of each capacitor in the fine delay means.

Claim 7

The ring-register controlled delay locked loop as recited in claim 3 , wherein the output clock signal generating means includes: a backward counter connected to the backward ring delay means for counting circulation of delay of the internal clock signal; a forward counter connected to the register means; and an internal clock signal output means having a count comparator to compare count values from the backward counter and the forward counter and for outputting the circularly delayed internal clock signal.

Claim 8

A ring-register controlled delay locked loop comprising: a skew detecting means receiving an internal clock signal and for outputting an internal clock synchronizing signal, which is synchronized with the received internal clock, and a delayed pulse corresponding to an amount of delay in a delay model; a phase detecting means for comparing an external clock signal with an output clock signal which is fed back from an output terminal of the ring-register controlled delay locked loop and producing a control signal in order to synchronize the external clock signal with the output clock signal; a fine delay means for carrying out a fine delay of the internal clock signal in response to the control signal from the phase detecting means or for bypassing the control signal from the phase detecting means; a coarse delay means having a plurality of unit delayers which are coupled to each other in a ring type, for coarsely delaying the delayed internal clock signal from the fine delay means in response to the internal clock synchronizing signal and the delayed pulse from the skew detecting means and the bypassed control signal from the fine delay means; an output clock signal generating means for the output clock signal when a desired delay is achieved in the coarse delay means; and a delay model for delaying the output clock signal and transferring the delayed output clock signal to the phase detecting means.

Claim 9

A ring-register controlled delay locked loop comprising: a skew detecting means receiving an internal clock signal and for outputting an internal clock synchronizing signal, which is synchronized with the received internal clock, and a delayed pulse corresponding to an amount of delay in a delay model; a phase detecting means for comparing an external clock signal with an output clock signal which is fed back from an output terminal of the ring-register controlled delay locked loop and producing a control signal in order to synchronize the external clock signal with the output clock signal; a fine delay means for carrying out a fine delay of the internal clock signal in response to the control signal from the phase detecting means or for bypassing the control signal from the phase detecting means; a coarse delay means having a plurality of unit delayers which are coupled to each other in a ring type, for coarsely delaying the delayed internal clock signal from the fine delay means in response to the internal clock synchronizing signal and the delayed pulse from the skew detecting means and the bypassed control signal from the fine delay means; an output clock signal generating means for the output clock signal when a desired delay is achieved in the coarse delay means; and a delay model for delaying the output clock signal and transferring the delayed output clock signal to the phase detecting means.

Claim 10

The ring-register controlled delay locked loop as recited in claim 7 , wherein the fine delay means includes: a fine delay line for delaying the internal clock signal by providing capacitive load to the internal clock signal, having a plurality of capacitors connected to a signal path of the internal clock signal; and a control means for selectively connecting the capacitors to the signal path of the internal clock signal in response to the control signal from the phase detecting means or for bypassing the control signal from the phase detecting means.

Claim 11

The ring-register controlled delay locked loop as recited in claim 8 , wherein the coarse delay means includes: a forward ring delay means having a plurality of delay stages, which are circularly connected to each other, for coarsely delaying the internal clock synchronizing signal from the skew detecting means by an amount of delay in the delay model; a backward ring delay means having a plurality of delay stages, which are circularly connected to each other, for coarsely delaying the delayed internal clock signal by the fine delay means; and a register means for controlling an amount of delay of the internal clock signal from the fine delay means in the circularly connected delay stages in response to the bypassed control signal from the phase detecting means and for storing a position of the delay stage corresponding to the current circulating delay pulse.

Claim 12

The ring-register controlled delay locked loop as recited in claim 9 , wherein each of the delay stages of the backward ring delay means includes: a first NAND gate receiving an output signal from the register means and the internal clock signal from the fine delay means; a second NAND gate receiving an output signal from the first NAND gate and an output signal from the circularly connected delay stage; and a third NAND gate receiving an output signal from the second NAND gate and a reset signal.

Claim 13

The ring-register controlled delay locked loop as recited in claim 9 , wherein each of the delay stages of the forward ring delay means includes: a first NAND gate receiving a first output signal from the skew detecting means and an output signal from the circularly connected delay stage; and a second NAND gate receiving a second output signal from the first NAND gate and an output signal from the circularly connected delay stage.

Claim 14

The ring-register controlled delay locked loop as recited in claim 9 , wherein the coarse delay means satisfies the following relationship: |τ FD −τ VAR,max |≦τ FD where τ CD is a delay time in the delay stage of the coarse delay means, τ VAR,max is a maximum delay time in the fine delay means, and τ CD is a delay time of each capacitor in the fine delay means.

Claim 15

The ring-register controlled delay locked loop as recited in claim 12 , wherein the output clock signal generating means includes: a backward counter connected to the backward ring delay means for counting circulation of delay of the internal clock signal; a forward counter connected to the register means for counting circulation of the delayed internal clock signal in the forward ring delay means and for detecting a position of the delay stage corresponding to the current circulating pulse; and an internal clock signal output means having a count comparator to compare count values from the backward counter and the forward counter and for outputting the circularly delayed internal clock signal.

Claim 16

A ring-register controlled delay locked loop comprising: a skew detecting means receiving an internal clock signal and for outputting an internal clock synchronizing signal, which is synchronized with the received internal clock, and a delayed pulse corresponding to an amount of delay in a delay model; a phase detecting means for comparing the internal clock signal with an output clock signal which is fed back from an output terminal of the ring-register controlled delay locked loop and producing a control signal in order to synchronize the internal clock signal with the output clock signal; a fine delay means for carrying out a fine delay of the internal clock signal in response to the control signal from the phase detecting means or for bypassing the control signal from the phase detecting means; a coarse delay means having a plurality of unit delayers which are coupled to each other in a ring type, for coarsely delaying the delayed internal clock signal from the fine delay means in response to the internal clock synchronizing signal and the delayed pulse from the skew detecting means and the bypassed control signal from the fine delay means; an output clock signal generating means for the output clock signal when a desired delay is achieved in the coarse delay means; and a delay model for delaying the output clock signal and transferring the delayed output clock signal to the phase detecting means.

Claim 17

A ring-register controlled delay locked loop comprising: a skew detecting means receiving an internal clock signal and for outputting an internal clock synchronizing signal, which is synchronized with the received internal clock, and a delayed pulse corresponding to an amount of delay in a delay model; a phase detecting means for comparing the internal clock signal with an output clock signal which is fed back from an output terminal of the ring-register controlled delay locked loop and producing a control signal in order to synchronize the internal clock signal with the output clock signal; a fine delay means for carrying out a fine delay of the internal clock signal in response to the control signal from the phase detecting means or for bypassing the control signal from the phase detecting means; a coarse delay means having a plurality of unit delayers which are coupled to each other in a ring type, for coarsely delaying the delayed internal clock signal from the fine delay means in response to the internal clock synchronizing signal and the delayed pulse from the skew detecting means and the bypassed control signal from the fine delay means; an output clock signal generating means for the output clock signal when a desired delay is achieved in the coarse delay means; and a delay model for delaying the output clock signal and transferring the delayed output clock signal to the phase detecting means.

Claim 18

A ring-register controlled delay locked loop comprising: a skew detecting means receiving an internal clock signal and for outputting an clock synchronizing signal, which is synchronized with the received internal clock signal, and a delayed pulse corresponding to an amount of delay in a delay model; a phase detecting means for comparing an external clock signal with an output clock signal which is fed back from an output terminal of the ring-register controlled delay locked loop and producing a first control signal in order to synchronize the external clock signal with the output clock signal; a coarse delay means having a plurality of unit delayers which are coupled to each other in a ring type, for coarsely delaying the delayed internal clock signal from the fine delay means in response to the clock synchronizing signal and the delayed pulse from the skew detecting means and a second control signal; an output clock signal generating means for generating the output clock signal while the coarse delay is required in the coarse delay means; a fine delay means for carrying out a fine delay of the internal clock signal in response to the first control signal from the phase detecting means or for bypassing the first control signal from the phase detecting means and then producing the second control signal; and a delay model for delaying the output clock signal and transferring the delayed output clock signal to the phase detecting means.

Claim 19

A ring-register controlled delay locked loop comprising: a skew detecting means receiving an internal clock signal and for outputting an clock synchronizing signal, which is synchronized with the received internal clock signal, and a delayed pulse corresponding to an amount of delay in a delay model; a phase detecting means for comparing an external clock signal with an output clock signal which is fed back from an output terminal of the ring-register controlled delay locked loop and producing a first control signal in order to synchronize the external clock signal with the output clock signal; a coarse delay means having a plurality of unit delayers which are coupled to each other in a ring type, for coarsely delaying the delayed internal clock signal from the fine delay means in response to the clock synchronizing signal and the delayed pulse from the skew detecting means and a second control signal; an output clock signal generating means for generating the output clock signal while the coarse delay is required in the coarse delay means; a fine delay means for carrying out a fine delay of the internal clock signal in response to the first control signal from the phase detecting means or for bypassing the first control signal from the phase detecting means and then producing the second control signal; and a delay model for delaying the output clock signal and transferring the delayed output clock signal to the phase detecting means.

Claim 20

A ring-register controlled delay locked loop comprising: a skew detecting means receiving an internal clock signal and for outputting an clock synchronizing signal, which is synchronized with the received internal clock signal, and a delayed pulse corresponding to an amount of delay in a delay model; a phase detecting means for comparing the internal clock signal with an output clock signal which is fed back from an output terminal of the ring-register controlled delay locked loop and producing a first control signal in order to synchronize the internal clock signal with the output clock signal; a coarse delay means having a plurality of unit delayers which are coupled to each other in a ring type, for coarsely delaying the delayed internal clock signal from the fine delay means in response to the clock synchronizing signal and the delayed pulse from the skew detecting means and a second control signal; an output clock signal generating means for generating the output clock signal while the coarse delay is required in the coarse delay means; a fine delay means for carrying out a fine delay of the internal clock signal in response to the first control signal from the phase detecting means or for bypassing the first control signal from the phase detecting means and then producing the second control signal; and a delay model for delaying the output clock signal and transferring the delayed output clock signal to the phase detecting means.

Claim 21

A ring-register controlled delay locked loop comprising: a skew detecting means receiving an internal clock signal and for outputting an clock synchronizing signal, which is synchronized with the received internal clock signal, and a delayed pulse corresponding to an amount of delay in a delay model; a phase detecting means for comparing the internal clock signal with an output clock signal which is fed back from an output terminal of the ring-register controlled delay locked loop and producing a first control signal in order to synchronize the internal clock signal with the output clock signal; a coarse delay means having a plurality of unit delayers which are coupled to each other in a ring type, for coarsely delaying the delayed internal clock signal from the fine delay means in response to the clock synchronizing signal and the delayed pulse from the skew detecting means and a second control signal; an output clock signal generating means for generating the output clock signal while the coarse delay is required in the coarse delay means; a fine delay means for carrying out a fine delay of the internal clock signal in response to the first control signal from the phase detecting means or for bypassing the first control signal from the phase detecting means and then producing the second control signal; and a delay model for delaying the output clock signal and transferring the delayed output clock signal to the phase detecting means.

Claim 22

The ring-register controlled delay locked loop as recited in claim 16 , wherein the fine delay means includes: a fine delay line for delaying the internal clock signal by providing capacitive load to the internal clock signal, having a plurality of capacitors connected to a signal path of the internal clock signal; and a control means for selectively connecting the capacitors to the signal path of the internal clock signal in response to the first control signal from the phase detecting means or for bypassing the first control signal from the phase detecting means.

Claim 23

The ring-register controlled delay locked loop as recited in claim 17 , wherein the coarse delay means includes: a forward ring delay means having a plurality of delay stages, which are circularly connected to each other, for coarsely delaying the internal clock synchronizing signal from the skew detecting means by an amount of delay in the delay model; a backward ring delay means having a plurality of delay stages, which are circularly connected to each other, for coarsely delaying the internal clock signal by the fine delay means; and a register means for controlling an amount of delay of the internal clock signal from the fine delay means in the circularly connected delay stages in response to the bypassed control signal from the phase detecting means and for storing a position of the delay stage corresponding to the current circulating delay pulse.

Claim 24

The ring-register controlled delay locked loop as recited in claim 18 , wherein each of the delay stages of the backward ring delay means includes: a first NAND gate receiving an output signal from the register means and the internal clock signal from the fine delay means; a second NAND gate receiving an output signal from the first NAND gate and an output signal from the circularly connected delay stage; and a third NAND gate receiving an output signal from the second NAND gate and a reset signal.

Claim 25

The ring-register controlled delay locked loop as recited in claim 19 , wherein each of the delay stages of the forward ring delay means includes: a first NAND gate receiving a first output signal from the skew detecting means and an output signal from the circularly connected delay stage; and a second NAND gate receiving a second output signal from the first NAND gate and an output signal from the circularly connected delay stage.

Claim 26

The ring-register controlled delay locked loop as recited in claim 18 , wherein the coarse delay means satisfies the following relationship: |τ FD −τ VAR,max |≦τ FD where τ CD is a delay time in the delay stage of the coarse delay means, τ VAR,max is a maximum delay time in the fine delay means, and τ CD is a delay time of each capacitor in the fine delay means.

Claim 27

The ring-register controlled delay locked loop as recited in claim 21 , wherein the output clock signal generating means includes: a backward counter connected to the backward ring delay means for counting circulation of delay of the internal clock signal; a forward counter connected to the register means for counting circulation of the delayed internal clock signal in the forward ring delay means and for detecting a position of the delay stage corresponding to the current circulating pulse; and an internal clock signal output means having a count comparator to compare count values from the backward counter and the forward counter and for outputting the circularly delayed internal clock signal.

Claim 28

The ring-register controlled delay locked loop as recited in claim 16 , wherein the fine delay means includes: a phase mixer for mixing the internal clock signal and a delayed internal clock signal which is delayed by a delay time in the coarse delay means and for dividing the unit delay time of the coarse delay means into a plurality of fine delay time; and a control means for selectively connecting the capacitors to the signal path of the internal clock signal in response to the first control signal from the phase detecting means or for bypassing the first control signal from the phase detecting means.

Claim 29

The ring-register controlled delay locked loop as recited in claim 23 , wherein the fine delay line includes a plurality of delayers, which are in series connected to each other and each of has the same delay time as the unit delayer in the coarse delay mean.

Claim 30

A ring-register controlled delay locked loop comprising: a first delay group including a plurality of unit delay elements which are lineally coupled to each other for delaying an input clock signal; a second delay group including a plurality of unit delay elements which are circularly coupled to each other for delaying an output signal from the first delay group; a first control means for determining an amount of lineal delay in the first delay group; and a second control means for determining an amount of circular delay in the first delay group.

Claim 31

A ring-register controlled delay locked loop comprising: a first delay group including a plurality of unit delay elements which are lineally coupled to each other for delaying an input clock signal; a second delay group including a plurality of unit delay elements which are circularly coupled to each other for delaying an output signal from the first delay group; a first control means for determining an amount of lineal delay in the first delay group; and a second control means for determining an amount of circular delay in the first delay group.

Claim 32

The ring-register controlled delay locked loop as recited in claim 25 , further comprising a skew detecting means for receiving the input clock signal and for outputting an internal clock synchronizing signal, which is synchronized with the received internal clock, and a delayed pulse corresponding to an amount of delay in a delay model.

Claim 33

The ring-register controlled delay locked loop as recited in claim 25 , wherein each of the unit delay elements in the first delay group has the same delay time as each of the of unit delay elements in the second delay group.

Claim 34

Aring-register controlled delay locked loop comprising: a first delay group including at least one unit delay element for delaying an input clock signal; a phase modifying means for modifying an output signals from the first delay group; a second delay group including a plurality of unit delay elements which are circularly coupled to each other for delaying an output signal from the first delay group; a first control means for determining an amount of lineal delay in the first delay group; and a second control means for determining an amount of circular delay in the second delay group.

Claim 35

Aring-register controlled delay locked loop comprising: a first delay group including at least one unit delay element for delaying an input clock signal; a phase modifying means for modifying an output signals from the first delay group; a second delay group including a plurality of unit delay elements which are circularly coupled to each other for delaying an output signal from the first delay group; a first control means for determining an amount of lineal delay in the first delay group; and a second control means for determining an amount of circular delay in the second delay group.

Claim 36

The ring-register controlled delay locked loop as recited in claim 27 , further comprising a skew detecting means for receiving the input clock signal and for outputting an internal clock synchronizing signal, which is synchronized with the received internal clock, and a delayed pulse corresponding to an amount of delay in a delay model.

Claim 39

The method as recited in claim 30 , wherein a delay time of the unit delay in the first delay group is substantially the same as that in the second delay group.

Claim 40

The method as recited in claim 30 , wherein a delay time of the unit delay in the first delay group is smaller than that in the second delay group.