US6072743A
Expired / Lapsed
US
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High speed operable semiconductor memory device with memory blocks arranged about the center
Assignee: Renesas Electronics Corp
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Filing: 1998-07-07
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Granted: 2000-06-06
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Expires: 2018-07-07
Abstract
Abstract A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.
Inventors
- 👤 Teruhiko Amano
- 👤 Takahiro Tsuruda
- 👤 Kazutami Arimoto
- 👤 Tetsushi Tanizaki
- 👤 Takeshi Fujino
- 👤 Mitsuya Kinoshita
- 👤 Fukashi Morishita
- 👤 Mako Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:04
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C11/4097; G11C5/00; G11C5/02; G11C5/025; G11C7/18; G11C8/00; G11C8/12; G11C8/14; G11C11/408
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
208 words
A semiconductor memory device formed at a memory region of a main surface of a semiconductor substrate, comprising: a plurality of memory blocks arranged to surround the center of the memory region of the main surface of said semiconductor substrate, each said memory block including: (a) a plurality of word lines; (b) a plurality of bit lines crossing said plurality of word lines; (c) a plurality of memory cells corresponding to crossings of said plurality of word lines and said plurality of bit lines; (d) a row decoder connected to said plurality of word lines; and (e) a column decoder selecting a bit line from among said plurality of bit lines; and a control circuit arranged at a center portion of the memory region of said main surface of said semiconductor substrate for providing control signal to said plurality of memory blocks, said control circuit including: (a) a master control circuit arranged at a center of said control circuit and generating a reference signal by which all of said plurality of memory blocks operate accordingly; and (b) a plurality of local control circuits arranged to surround said master control circuit, each local control circuit receiving said reference signal to output said control signal to a corresponding memory block.
Claim 2
Dependent Claim
208 words
A semiconductor memory device formed at a memory region of a main surface of a semiconductor substrate, comprising: a plurality of memory blocks arranged to surround the center of the memory region of the main surface of said semiconductor substrate, each said memory block including: (a) a plurality of word lines; (b) a plurality of bit lines crossing said plurality of word lines; (c) a plurality of memory cells corresponding to crossings of said plurality of word lines and said plurality of bit lines; (d) a row decoder connected to said plurality of word lines; and (e) a column decoder selecting a bit line from among said plurality of bit lines; and a control circuit arranged at a center portion of the memory region of said main surface of said semiconductor substrate for providing control signal to said plurality of memory blocks, said control circuit including: (a) a master control circuit arranged at a center of said control circuit and generating a reference signal by which all of said plurality of memory blocks operate accordingly; and (b) a plurality of local control circuits arranged to surround said master control circuit, each local control circuit receiving said reference signal to output said control signal to a corresponding memory block.
Claim 3
Dependent Claim
58 words
The semiconductor memory device according to claim 1, wherein said control circuit further comprises a clock input terminal for receiving an external clock, wherein said master control circuit includes an internal clock generation circuit generating an internal clock according to said external clock, and each said local control circuit provides said control signal according to said internal clock.
Claim 4
Dependent Claim
36 words
The semiconductor memory device according to claim 2, wherein said internal clock generation circuit comprises a PLL (Phase Locked Loop) circuit receiving said external clock to generate said internal clock in phase with said external clock.
Claim 5
Dependent Claim
41 words
The semiconductor memory device according to claim 2, wherein said internal clock generation circuit comprises a DLL (Delayed Locked Loop) circuit receiving and delaying said external clock to generate said internal clock having a predetermined phase difference from said external clock.
Claim 6
Dependent Claim
74 words
The semiconductor memory device according to claim 1, wherein said memory region has a rectangular shape, each of said plurality of memory blocks has a rectangular shape, said center portion has a rectangular shape, said plurality of local control circuits are provided corresponding to said plurality of memory blocks, and each said local control circuit is arranged at one of four corners of said center portion that is closest to a corresponding memory block.
Claim 7
Dependent Claim
46 words
The semiconductor memory device according to claim 5, wherein said semiconductor memory device has a memory capacity of 2 2m+1 bits, said plurality of memory blocks all have equal memory capacity, and each said memory block has a rectangular shape with an aspect ratio of 1:2.
Claim 8
Dependent Claim
132 words
The semiconductor memory device according to claim 5, further comprising a data bus provided corresponding to each said memory block and having at least one portion arranged along said column decoder of a corresponding one of said memory blocks, wherein said control circuit further comprises a pad receiving an externally applied address signal, and a pad receiving an externally applied data signal, said master control circuit comprises a predecode circuit predecoding said address signal, each said local control circuit comprises an output circuit providing an output of said predecode circuit to said row decoder according to an activation signal of said corresponding memory block, and said row decoder and column decoder are provided along first and second sides out of four sides of said memory block, closest to said local control circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-06 | 2003-12-06 | 2004-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-06 | 2007-12-06 | 2008-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-06 | 2011-12-06 | 2012-06-06 | $7700.00 | Window Closed / Lapsed |