US6034918A
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US
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Method of operating a memory having a variable data output length and a programmable register
Assignee: Rambus Inc
•
Filing: 1999-02-19
•
Granted: 2000-03-07
•
Expires: 2019-02-19
Abstract
Abstract A method of controlling a memory device is disclosed wherein the memory device includes a plurality of memory cells. The method comprises providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be output onto a bus in response to a read request. The method further includes issuing a first read request to the memory device, wherein in response to the first read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to an external clock signal. In one preferred embodiment, the method may include providing a code which is representative of a number of clock cycles of the first and second external clock which are to transpire before data is output by the memory device onto the bus. The memory device stores the code in a programmable register on the memory device. In this preferred embodiment, the first amount of data corresponding to the first block size information is output after the number of clock cycles of the external clock transpire.
Inventors
- 👤 Michael Farmwald
- 👤 Mark Horowitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:20
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G06; G06F; G06F11/00; G06F11/006; G06F12/00; G06F12/02; G06F12/0215; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F12/0684; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1668; G06F13/1678; G06F13/1689; G06F13/1694; G06F13/36; G06F13/368; G06F13/376; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4096; G11C29/00; G11C29/70; G11C29/88; G11C5/00; G11C5/02; G11C5/04; G11C5/06; G11C5/063; G11C5/066; G11C7/1006; G11C7/1012; G11C7/1015; G11C7/1045; G11C7/1057; G11C7/1069; G11C7/1072; G11C7/1078; G11C7/1084; G11C7/22; G11C7/222; G11C7/225; G11C8/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G11C2207/00; G11C2207/10; G11C2207/105; G11C2207/108; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
108 words
A method of controlling a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises: providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be output by the memory device onto a bus in response to a read request; and issuing a first read request to the memory device, wherein in response to the first read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to an external clock signal.
Claim 2
Independent Claim
108 words
A method of controlling a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises: providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be output by the memory device onto a bus in response to a read request; and issuing a first read request to the memory device, wherein in response to the first read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to an external clock signal.
Claim 3
Dependent Claim
81 words
The method of claim 1 wherein first block size information further defines a first amount of data to be input by the memory device from the bus in response to a write request, the method further including issuing a first write request to the memory device wherein, in response to the first write request, the memory device inputs the first amount of data corresponding to the first block size information from the bus synchronously with respect to the external clock signal.
Claim 4
Dependent Claim
88 words
The method of claim 2 further including: providing second block size information to the memory device, wherein the second block size information defines a second amount of data to be input by the memory device from the bus in response to a write request; and issuing the second write request to the memory device, wherein in response to the second write request, the memory device inputs the amount of data corresponding to the second block size information from the bus synchronously with respect to the external clock signal.
Claim 5
Dependent Claim
22 words
The method of claim 2 wherein the first block size information and the first write request are included in a request packet.
Claim 6
Dependent Claim
23 words
The method of claim 4 wherein the first block size information and the first write request are included in the same request packet.
Claim 7
Dependent Claim
51 words
The method of claim 1 further including issuing a second read request to the memory device, wherein in response to the second read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to the external clock signal.
Claim 8
Dependent Claim
84 words
The method of claim 6 further including: providing second block size information to the memory device, wherein the second block size information defines a second amount of data to be output onto the bus in response to a read request; and issuing a third request to the memory device, wherein in response to the third read request, the memory device outputs the second amount of data corresponding to the second block size information onto the bus synchronously with respect to the external clock signal.
Claim 9
Dependent Claim
48 words
The method of claim 1 further including providing a code which is representative of a delay time to transpire before data is output onto the bus after receipt of a read request, wherein the memory device stores the code in an access time register on the memory device.
Claim 10
Dependent Claim
33 words
The method of claim 8 further including receiving the external clock signal wherein the first amount of data corresponding to the first block size information is output in accordance with the delay time.
Claim 11
Dependent Claim
30 words
The method of claim 8 wherein the code represents a number of cycles of the external clock and wherein the number of cycles is a fraction or a whole number.
Claim 12
Dependent Claim
22 words
The method of claim 1 wherein the first block size information and the first read request are included in a request packet.
Claim 13
Dependent Claim
23 words
The method of claim 11 wherein the first block size information and the first read request are included in the same request packet.
Claim 14
Dependent Claim
30 words
The method of claim 11 wherein the first block size information is a binary representation of the amount of data to be output after receipt of the first read request.
Claim 15
Dependent Claim
24 words
The method of claim 11 wherein the first block size information is indicative of an amount of data corresponding to a page mode access.
Claim 16
Dependent Claim
42 words
The method of claim 11 wherein the external clock signal has a fixed frequency and wherein the first amount of data corresponding to the first block size information is output synchronously during a plurality of clock cycles of the external clock signal.
Claim 17
Dependent Claim
47 words
The method of claim 11 further including generating at least one internal clock signal using the external clock signal wherein the first amount of data corresponding to the first block size information is output onto the bus synchronously with respect to at least one internal clock signal.
Claim 18
Dependent Claim
17 words
The method of claim 16 wherein the internal clock signal is generated by a delay locked loop.
Claim 19
Independent Claim
110 words
A method of operation of a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of operation of the memory device comprises: receiving an external clock signal; receiving first block size information from a bus controller, wherein the first block size information defines a first amount of data to be output by the memory device onto a bus in response to a read request; receiving a first request from the bus controller; and outputting the first amount of data corresponding to the first block size information, in response to the first read request, onto the bus synchronously with respect to the external clock signal.
Claim 20
Independent Claim
110 words
A method of operation of a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of operation of the memory device comprises: receiving an external clock signal; receiving first block size information from a bus controller, wherein the first block size information defines a first amount of data to be output by the memory device onto a bus in response to a read request; receiving a first request from the bus controller; and outputting the first amount of data corresponding to the first block size information, in response to the first read request, onto the bus synchronously with respect to the external clock signal.
Claim 21
Dependent Claim
48 words
The method of claim 18 further including: receiving a second read request from the bus controller, and outputting the first amount of data corresponding to the first block size information, in response to the second read request, onto the bus synchronously with respect to the external clock signal.
Claim 22
Dependent Claim
78 words
The method of claim 18 wherein first block size information further defines a first amount of data to be input by the memory device from the bus in response to a write request, the method further including: receiving a first write request from the bus controller, and inputting the first amount of data corresponding to the first block size information, in response to the first write request, from the bus synchronously with respect to the external clock signal.
Claim 23
Dependent Claim
76 words
The method of claim 20 further including: receiving second block size information, wherein the second block size information defines a second amount of data to be input from the bus in response to a write request; and receiving the second write request from the bus controller; inputting the amount of data corresponding to the second block size information, in response to the second write request, from the bus synchronously with respect to the external clock signal.
Claim 24
Dependent Claim
22 words
The method of claim 20 wherein the first block size information and the first write request are included in a request packet.
Claim 25
Dependent Claim
23 words
The method of claim 22 wherein the first block size information and the first write request are included in the same request packet.
Claim 26
Dependent Claim
67 words
The method of claim 18 further including storing a delay time code in an access time register, the delay time code being representative of a number of clock cycles to transpire before data is output onto the bus after receipt of a read request and wherein the first amount of data corresponding to the first block size information is output in accordance with the delay time code.
Claim 27
Dependent Claim
25 words
The method of claim 24 wherein the delay time code is stored in the access time register after power is applied to the memory device.
Claim 28
Dependent Claim
18 words
The method of claim 25 wherein the number of clock cycles is a fraction or a whole number.
Claim 29
Dependent Claim
22 words
The method of claim 18 wherein the first block size information and the first read request are included in a request packet.
Claim 30
Dependent Claim
23 words
The method of claim 27 wherein the first block size information and the first read request are included in the same request packet.
Claim 31
Dependent Claim
31 words
The method of claim 18 wherein the first block size information is a binary representation of the first amount of data to be output after receipt of the first read request.
Claim 32
Dependent Claim
28 words
The method of claim 18 wherein the first block size information is indicative of an amount of data corresponding to one of a plurality of page mode accesses.
Claim 33
Dependent Claim
42 words
The method of claim 18 wherein the external clock signal has a fixed frequency and wherein the first amount of data corresponding to the first block size information is output synchronously during a plurality of clock cycles of the external clock signal.
Claim 34
Dependent Claim
19 words
The method of claim 31 further including automatically precharging the synchronous memory device after executing the first read request.
Claim 35
Dependent Claim
52 words
The method of claim 18 further including generating at least one internal clock signal using a delay locked loop and the external clock signal wherein the first amount of data corresponding to the first block size information is output onto the bus synchronously with respect to at least one internal clock signal.
Claim 36
Independent Claim
182 words
A method of operation of a synchronous memory device, wherein the memory device includes a plurality of memory cells and a time delay register, the method of operation of the memory device comprises: storing a value in the time delay register, the value being representative of a number of external clock cycles to transpire after which the memory device responds to a read request; receiving an external clock signal wherein the external clock signal has a fixed frequency; receiving block size information from a bus controller, wherein the block size information defines a first amount of data to be output by the memory device onto the bus in response to a read request; receiving a first read request from the bus controller; outputting the first amount of data corresponding to the block size information onto the bus in response to the first read request, wherein the memory device outputs the data synchronously with respect to the external clock signal, during a plurality of clock cycles of the external clock signal and in accordance with the value stored in the time delay register.
Claim 37
Independent Claim
182 words
A method of operation of a synchronous memory device, wherein the memory device includes a plurality of memory cells and a time delay register, the method of operation of the memory device comprises: storing a value in the time delay register, the value being representative of a number of external clock cycles to transpire after which the memory device responds to a read request; receiving an external clock signal wherein the external clock signal has a fixed frequency; receiving block size information from a bus controller, wherein the block size information defines a first amount of data to be output by the memory device onto the bus in response to a read request; receiving a first read request from the bus controller; outputting the first amount of data corresponding to the block size information onto the bus in response to the first read request, wherein the memory device outputs the data synchronously with respect to the external clock signal, during a plurality of clock cycles of the external clock signal and in accordance with the value stored in the time delay register.
Claim 38
Dependent Claim
11 words
The method of claim 32 wherein the value is hard wired.
Claim 39
Dependent Claim
21 words
The method of claim 32 wherein the block size information and the first read request are included in the same request.
Claim 40
Dependent Claim
93 words
The method of claim 32 further including: receiving a second read request from the bus controller wherein the block size information and the second read request are included in the same request; outputting the first amount of data corresponding to the block size information onto the bus in response to the second read request; and wherein the memory device outputs the data synchronously with respect to the external clock signal, during a plurality of clock cycles of the external clock signal and in accordance with the valued stored in the time delay register.
Claim 41
Dependent Claim
22 words
The method of claim 32 wherein the value represents a fraction or whole number of clock cycles of the external clock signal.
References Cited (Backward Citations)
US3821715A
Cited
US4092665A
Cited
US4247817A
Cited
US4183095A
Cited
US4315308A
Cited
US4445204A
Cited
US4519034A
Cited
US4734880A
Cited
US4570220A
Cited
US4675850A
Cited
US4951251A
Cited
US4680738A
Cited
US4788667A
Cited
US4920483A
Cited
US4845664A
Cited
US4799199A
Cited
US5140688A
Cited
US5016226A
Cited
US4953128A
Cited
US4821226A
Cited
US4807189A
Cited
US4882712A
Cited
US4928265A
Cited
US4916670A
Cited
US5361277A
Cited
US5301278A
Cited
US5109498A
Cited
US5206833A
Cited
US4975872A
Cited
US5148523A
Cited
US5142637A
Cited
US5018111A
Cited
US4937734A
Cited
US4954987A
Cited
US5083296A
Cited
US5107465A
Cited
US4970418A
Cited
US5077693A
Cited
US5390149A
Cited
US5847997A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-07 | 2003-09-06 | 2004-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-07 | 2007-09-06 | 2008-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-07 | 2011-09-06 | 2012-03-07 | $7700.00 | Window Closed / Lapsed |