US6101137A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device having delay locked loop (DLL)
Assignee: Samsung Electronics Co Ltd
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Filing: 1999-06-23
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Granted: 2000-08-08
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Expires: 2019-06-23
Abstract
Abstract A semiconductor memory device having a delay locked loop includes a delay locked loop and a voltage supply unit. The delay locked loop reduces the skew between a clock and data. The voltage supply unit supplies the voltages required by the delay locked loop when the delay locked loop is operating and is deactivated when the delay locked loop is not operating.
Inventors
- 👤 Jae-Gu Roh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:15
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03L7/0802; H03L7/081; H03L7/0812
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
115 words
A semiconductor memory device having a mode requiring a delay locked loop operation and a mode not requiring the delay locked loop operation comprising: a reference voltage generator for generating a reference voltage; a delay locked loop reference voltage generator for receiving a control signal and the reference voltage and for generating a delay locked loop reference voltage if the control signal is disabled, the delay locked loop reference voltage generator being deactivated if the control signal is enabled; and a switch connected between the reference voltage generator and the delay locked loop reference voltage generator for transmitting the reference voltage to the delay locked loop reference voltage generator in response to the control signal.
Claim 2
Dependent Claim
115 words
A semiconductor memory device having a mode requiring a delay locked loop operation and a mode not requiring the delay locked loop operation comprising: a reference voltage generator for generating a reference voltage; a delay locked loop reference voltage generator for receiving a control signal and the reference voltage and for generating a delay locked loop reference voltage if the control signal is disabled, the delay locked loop reference voltage generator being deactivated if the control signal is enabled; and a switch connected between the reference voltage generator and the delay locked loop reference voltage generator for transmitting the reference voltage to the delay locked loop reference voltage generator in response to the control signal.
Claim 3
Dependent Claim
14 words
The semiconductor memory device of claim 1, wherein the switch is a transmission gate.
Claim 4
Dependent Claim
64 words
The semiconductor memory device of claim 1, wherein the delay locked loop reference voltage generator comprises: a differential amplification unit for receiving the reference voltage and generating the delay locked loop reference voltage; and a logic unit for receiving the control signal and preventing generation of the delay locked loop reference voltage by deactivating the differential amplification unit when the control signal is enabled.
Claim 5
Dependent Claim
37 words
The semiconductor memory device of claim 1, further comprising: an internal voltage generator for receiving the control signal and the delay locked loop reference voltage and generating an internal supply voltage if the control signal is disabled.
Claim 6
Dependent Claim
60 words
The semiconductor memory device of claim 4, wherein the internal voltage generator comprises: a differential amplification unit for receiving the delay locked loop reference voltage and generating the internal supply voltage; and a control unit for receiving the control signal and preventing generation of the internal supply voltage by deactivating the differential amplification unit when the control signal is enabled.
Claim 7
Independent Claim
86 words
A method for operating a delay locked loop comprising: providing a control signal which is disabled when the delay locked loop is in use and enabled when the delay locked loop is not in use; generating a delay locked loop reference voltage only when the control signal is disabled; generating an internal supply voltage only when the control signal is disabled; and transmitting the delay locked loop reference voltage and the internal supply voltage to the delay locked loop only when the control signal is disabled.
Claim 8
Independent Claim
86 words
A method for operating a delay locked loop comprising: providing a control signal which is disabled when the delay locked loop is in use and enabled when the delay locked loop is not in use; generating a delay locked loop reference voltage only when the control signal is disabled; generating an internal supply voltage only when the control signal is disabled; and transmitting the delay locked loop reference voltage and the internal supply voltage to the delay locked loop only when the control signal is disabled.
Claim 9
Dependent Claim
30 words
The method of claim 6, further comprising the step of generating a second reference voltage, wherein the second reference voltage is used to generate the delay locked loop reference voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-08 | 2004-02-07 | 2004-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-08 | 2008-02-07 | 2008-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-08 | 2012-02-07 | 2012-08-08 | $7700.00 | Window Closed / Lapsed |