Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device comprising: a plurality of functional blocks, each comprising: a DLL circuit for outputting a first clock signal; at least one wiring portion, one end of which is connected to an output end of said DLL circuit for allowing said first clock signal to pass therethrough; and at least one load circuit for receiving said first clock signal from said DLL circuit via said wiring portion, wherein said DLL circuit receives a reference clock signal and a second clock signal outputted from the other end of said wiring portion and outputs said first clock signal so that a phase difference between the reference clock signal and the second clock signal is a predetermined value.

Claim 3

A semiconductor integrated circuit device as set forth in claim 1, wherein at least one functional block of said plurality of functional blocks has a plurality of wiring portions, each of which is said wiring portion, each of said wiring portions being provided with at least one load circuit corresponding to each of said wiring portions, one end of each of said plurality of wiring portions being short-circuited to receive an output of said DLL circuit, and the other end of each of said plurality of wiring portions being short-circuited to be connected to an input end of said DLL circuit, to which said second clock signal is inputted.

Claim 4

A semiconductor integrated circuit device as set forth in claim 2, wherein the other end of each of said wiring portions of said plurality of functional blocks is short-circuited, and which further comprises a PLL circuit for producing said reference clock signal on the basis of said second clock signal transmitted from the short-circuit end and a clock signal transmitted from the outside, to transmit said reference clock signal to said DLL circuit of each of said plurality of functional blocks.

Claim 5

A semiconductor integrated circuit device as set forth in claim 3, wherein said DLL circuit comprises: a delay circuit for producing a plurality of delay signals, which have different lags from said reference clock signal, on the basis of said reference clock signal; a phase comparator circuit for comparing a phase of said reference clock signal with a phase of said second clock signal transmitted from the other end of said wiring portion, to output a control signal for causing a phase difference of a predetermined value; and means for selecting one delay signal from said plurality of delay signals on the basis of said control signal to output the selected delay signal to said wiring portion.

Claim 6

A semiconductor integrated circuit device as set forth in claim 4, wherein said delay circuit has a series circuit comprising a plurality of serially-connected delay elements.

Claim 7

A semiconductor integrated circuit device as set forth in claim 4, wherein said delay circuit has a plurality of series circuits, each of which comprises a plurality of serially-connected delay elements, said plurality of series circuits being connected to each other in parallel, each of said plurality of series circuits having different lags.

Claim 8

A semiconductor integrated circuit device as set forth in claim 1, wherein the other end of each of said wiring portions of said plurality of functional blocks is short-circuited, and which further comprises a PLL circuit for producing said reference clock signal on the basis of said second clock signal transmitted from the short-circuit end and a clock signal transmitted from the outside, to transmit said reference clock signal to said DILL circuit of each of said plurality of functional blocks.

Claim 9

A semiconductor integrated circuit device as set forth in claim 7, wherein said DLL circuit comprises: a delay circuit for producing a plurality of delay signals, which have different lags from said reference clock signal, on the basis of said reference clock signal; a phase comparator circuit for comparing a phase of said reference clock signal with a phase of said second clock signal transmitted from the other end of said wiring portion, to output a control signal for causing a phase difference of a predetermined value; and means for selecting one delay signal from said plurality of delay signals on the basis of said control signal to output the selected delay signal to said wiring portion.

Claim 10

A semiconductor integrated circuit device as set forth in claim 1, wherein said DLL circuit comprises: a delay circuit for producing a plurality of delay signals, which have different lags from said reference clock signal, on the basis of said reference clock signal; a phase comparator circuit for comparing a phase of said reference clock signal with a phase of said second clock signal transmitted from the other end of said wiring portion, to output a control signal for causing a phase difference of a predetermined value; and means for selecting one delay signal from said plurality of delay signals on the basis of said control signal to output the selected delay signal to said wiring portion.

Claim 11

A semiconductor integrated circuit device comprising: a plurality of functional blocks, each comprising: a DLL circuit for receiving a reference clock signal and at least one shift clock signal phase-shifted from said reference clock signal, to output a first clock signal; at least one wiring portion, one end of which is connected to an output end of said DLL circuit for allowing said first clock signal to pass therethrough; and at least one load circuit for receiving said first clock signal from said DLL circuit via said wiring portion, wherein said DLL circuit receives a reference clock signal and a second clock signal outputted from the other end of said wiring portion and outputs said first clock signal so that a phase difference between the reference clock signal and the second clock signal is a predetermined value.

Claim 12

A semiconductor integrated circuit device comprising: a plurality of functional blocks, each comprising: a DLL circuit for receiving a reference clock signal and at least one shift clock signal phase-shifted from said reference clock signal, to output a first clock signal; at least one wiring portion, one end of which is connected to an output end of said DLL circuit for allowing said first clock signal to pass therethrough; and at least one load circuit for receiving said first clock signal from said DLL circuit via said wiring portion, wherein said DLL circuit receives a reference clock signal and a second clock signal outputted from the other end of said wiring portion and outputs said first clock signal so that a phase difference between the reference clock signal and the second clock signal is a predetermined value.

Claim 13

A semiconductor integrated circuit device as set forth in claim 10, wherein at least one functional block of said plurality of functional blocks has a plurality of wiring portions, each of which is said wiring portion, each of said wiring portions being provided with at least one load circuit corresponding to each of said wiring portions, one end of each of said plurality of wiring portions being short-circuited to receive an output of said DLL circuit, and the other end of each of said plurality of wiring portions being short-circuited to be connected to an input end of said DLL circuit, to which said second clock signal is inputted.

Claim 14

A semiconductor integrated circuit device as set forth in claim 11, which further comprises a PLL circuit for producing said reference clock signal and said shift clock signal on the basis of a clock signal transmitted from the outside, to transmit said reference clock signal and said shift clock signal to said DLL circuit of each of said plurality of functional blocks.

Claim 15

A semiconductor integrated circuit device as set forth in claim 11, wherein said shift clock signal is a first shift clock signal delayed from said reference clock signal by a phase of 90 degrees, and wherein said DLL circuit comprises: shift clock producing means for producing a second shift clock signal delayed from said reference clock signal by a phase of 180 degree and a third shift clock signal delayed from said first shift clock signal by a phase of 180 degree, on the basis of said reference clock signal and said first shift clock signal; a selecting circuit for selecting one clock signal from said reference clock signal and said first through third shift clock signals on the basis of a command signal, to output the selected clock signal; a phase comparator circuit for comparing a phase of a second clock signal outputted from the other end of said wiring portion with a phase of said reference clock signal, to detect a phase lag of said second clock signal from said reference clock signal to transmit said command signal to said selecting circuit on the basis of said phase lag; and a delay circuit for applying a lag, which corresponds to said phase lag detected by said phase comparator circuit, to said clock signal outputted from said selecting circuit and for outputting the resulting clock signal to said wiring portion.

Claim 16

A semiconductor integrated circuit device as set forth in claim 10, which further comprises a PLL circuit for producing said reference clock signal and said shift clock signal on the basis of a clock signal transmitted from the outside, to transmit the produced signals to said DLL circuit of each of said plurality of functional blocks.

Claim 17

A semiconductor integrated circuit device as set forth in claim 10, wherein said shift clock signal is a first shift clock signal delay ed from said reference clock signal by a phase of 90 degrees, and wherein said DLL circuit comprises: shift clock producing means for producing a second shift clock signal delayed from said reference clock signal by a phase of 180 degree and a third shift clock signal delayed from said first shift clock signal by a phase of 180 degree, on the basis of said reference clock signal and said first shift clock signal; a selecting circuit for selecting one clock signal from said reference clock signal and said first through third shift clock signals on the basis of a command signal, to output the selected clock signal; a phase comparator circuit for comparing a phase of a second clock signal outputted from the other end of said wiring portion with a phase of said reference clock signal, to detect a phase lag of said second clock signal from said reference clock signal to transmit said command signal to said selecting circuit on the basis of said phase lag; and a delay circuit for applying a lag, which corresponds to said phase lag detected by said phase comparator circuit, to said clock signal outputted from said selecting circuit and for outputting the resulting clock signal to said wiring portion.