Method and apparatus for improving stability and lock time for synchronous circuits

Claim 2

A delay-locked loop, comprising: a delay line having first and second inputs and an output, said first input configured to receive an external clock signal via a clock input path and said output configured to couple with an output driver of a memory device; an I/O model having an output and an input, said input of said I/O model configured to couple with said output of said delay line via a clock distribution network of said memory device, said I/O model including an output driver delay model configured to model delay of said output driver; a phase detector having forward and feedback path inputs and an output operably coupled to said second input of said delay line, said forward path input coupled to said first input of said delay line and said feedback path input coupled to said output of said I/O model; and a timer circuit having an output and an input, said output of said timer circuit switchably coupled to said first input of said delay line and said input of said timer circuit operably coupled to said feedback path input of said phase detector, said timer circuit configured to generate a test signal on said output thereof and calculate a loop delay from receipt of said test signal on said input thereof.

Claim 3

The delay-locked loop, as recited in claim 1 , wherein said clock input path includes a multiplexer having a first input for coupling with said external clock signal and a second input for coupling with said output of said timer circuit, said multiplexer for alternatively switching said external clock signal and said test signal to an output coupled to said first input of said delay line.

Claim 4

The delay-locked loop, as recited in claim 2 , wherein said I/O model further comprises a clock input path delay model configured to model delay of said clock input path.

Claim 5

The delay-locked loop, as recited in claim 1 , wherein said phase detector is configured to suspend generation of an output signal during calculation of said loop delay by said timer circuit.

Claim 6

The delay-locked loop, as recited in claim 1 , wherein said phase detector is configured to generate an output at a period of, at most, once per loop delay.

Claim 7

The delay-locked loop, as recited in claim 1 , wherein said delay line is configured with a first delay path for inserting delay during an initialization mode of said phase detector and a second delay path for inserting delay during an operational mode of said delay-locked loop.

Claim 8

The delay-locked loop, as recited in claim 6 , wherein said first delay path is configured as a synchronous mirror delay.

Claim 9

A delay-locked loop, comprising: a forward delay path having an input configured to couple with an external clock signal and an output configured to couple with an output driver of a memory device, said forward delay path including an adjustable delay line configured to adjust delay of said external clock signal through said forward delay path; a feedback delay path having an output and an input, said input of said feedback delay path configured for coupling with said output driver of said memory device, said feedback delay path including a delay model of said output driver of said memory device; a phase detector having forward and feedback path inputs and an output operably coupled to said adjustable delay line, said forward path input coupled to said adjustable delay line and said feedback path input coupled to said output of said feedback delay path; and a timer circuit having an output and an input, said output of said timer circuit switchably coupled to said adjustable delay line and said input of said timer circuit operably coupled to said feedback path input of said phase detector, said timer circuit configured to generate a test signal on said output thereof and calculate a loop delay from receipt of said test signal on said input thereof.

Claim 10

A delay-locked loop, comprising: a forward delay path having an input configured to couple with an external clock signal and an output configured to couple with an output driver of a memory device, said forward delay path including an adjustable delay line configured to adjust delay of said external clock signal through said forward delay path; a feedback delay path having an output and an input, said input of said feedback delay path configured for coupling with said output driver of said memory device, said feedback delay path including a delay model of said output driver of said memory device; a phase detector having forward and feedback path inputs and an output operably coupled to said adjustable delay line, said forward path input coupled to said adjustable delay line and said feedback path input coupled to said output of said feedback delay path; and a timer circuit having an output and an input, said output of said timer circuit switchably coupled to said adjustable delay line and said input of said timer circuit operably coupled to said feedback path input of said phase detector, said timer circuit configured to generate a test signal on said output thereof and calculate a loop delay from receipt of said test signal on said input thereof.

Claim 11

The delay-locked loop, as recited in claim 8 , wherein said forward delay path includes a multiplexer having a first input for coupling with said external clock signal and a second input for coupling with said output of said timer circuit, said multiplexer for alternatively switching said external clock signal and said test signal to an output coupled to said adjustable delay line.

Claim 12

The delay-locked loop, as recited in claim 9 , wherein said feedback delay path further includes a second delay model configured to model delay of a portion of said forward delay path.

Claim 13

The delay-locked loop, as recited in claim 8 , wherein said phase detector is configured to suspend generation of an output signal during calculation of said loop delay by said timer circuit.

Claim 14

The delay-locked loop, as recited in claim 8 , wherein said phase detector is configured to generate an output at a period of, at most, once per loop delay.

Claim 15

The delay-locked loop, as recited in claim 8 , wherein said adjustable delay line is configured with a first delay path for inserting delay during an initialization mode of said phase detector and a second delay path for inserting delay during an operational mode of said delay-locked loop.

Claim 16

A memory device, comprising: a memory array with an output driver coupled thereto; and a delay-locked loop operably coupled between said output driver and configured to couple with an external clock signal, said delay-locked loop including forward and feedback delay paths, said delay-locked loop configured to switchably couple a test signal into said forward delay path and calculate a loop delay from receipt of said test signal from said feedback delay path, said delay-locked loop further including a phase detector configured to adapt a sampling rate responsive to said loop delay.

Claim 17

A memory device, comprising: a memory array with an output driver coupled thereto; and a delay-locked loop operably coupled between said output driver and configured to couple with an external clock signal, said delay-locked loop including forward and feedback delay paths, said delay-locked loop configured to switchably couple a test signal into said forward delay path and calculate a loop delay from receipt of said test signal from said feedback delay path, said delay-locked loop further including a phase detector configured to adapt a sampling rate responsive to said loop delay.

Claim 18

The memory device, as recited in claim 14 , wherein said feedback delay path comprises a delay model of said output driver of said memory device.

Claim 19

The memory device, as recited in claim 15 , wherein said feedback delay path further comprises a second delay model configured to model delay of an input portion of said forward delay path.

Claim 20

The memory device, as recited in claim 14 , wherein said forward delay path comprises an adjustable delay line configured to adjust delay of said external clock signal through said forward delay path.

Claim 21

The memory device, as recited in claim 17 , wherein said adjustable delay line is configured with a first delay path for inserting delay during an initialization mode of said phase detector and a second delay path for inserting a delay during an operational mode of said delay-locked loop.

Claim 22

The memory device, as recited in claim 18 , wherein said first delay path is configured as a synchronous mirror delay.

Claim 23

A memory device, comprising: a memory array; an output driver operably coupled to said memory array; and a delay-locked loop operably coupled to said output driver, said delay-locked loop including: a delay line configured to receive an external clock signal and to couple with said output driver; a feedback delay path having an output and coupled at an input with said output driver, said feedback delay path including a delay model of said output driver; a phase detector having forward and feedback path inputs and an output operably coupled to said delay line, said forward path input coupled to said delay line and said feedback path input coupled to said output of said feedback delay path; and a timer circuit switchably coupled to said delay line and said feedback path input of said phase detector, said timer circuit configured to generate a test signal on said delay line and calculate a loop delay from receipt of said test signal.

Claim 24

A memory device, comprising: a memory array; an output driver operably coupled to said memory array; and a delay-locked loop operably coupled to said output driver, said delay-locked loop including: a delay line configured to receive an external clock signal and to couple with said output driver; a feedback delay path having an output and coupled at an input with said output driver, said feedback delay path including a delay model of said output driver; a phase detector having forward and feedback path inputs and an output operably coupled to said delay line, said forward path input coupled to said delay line and said feedback path input coupled to said output of said feedback delay path; and a timer circuit switchably coupled to said delay line and said feedback path input of said phase detector, said timer circuit configured to generate a test signal on said delay line and calculate a loop delay from receipt of said test signal.

Claim 25

The memory device, as recited in claim 20 , further comprising a clock input path operably coupled between said delay line and said external clock signal.

Claim 26

The memory device, as recited in claim 21 , wherein said feedback delay path further includes a second delay model configured to model delay of said clock input path.

Claim 27

The memory device, as recited in claim 20 , wherein said phase detector is configured to suspend adjustments to said delay line during calculation of said loop delay by said timer circuit.

Claim 28

The memory device, as recited in claim 20 , further comprising a clock distribution network coupled between said delay line and said output driver.

Claim 29

An electronic system, comprising: a processor; at least one of an input device and an output device operably coupled to said processor; and a memory device operably coupled to said processor, said memory device including: a memory array with an output driver coupled thereto; and a delay-locked loop operably coupled between said output driver and configured to couple with an external clock signal, said delay-locked loop including forward and feedback delay paths, said delay-locked loop configured to switchably couple a test signal into said forward delay path and calculate a loop delay from receipt of said test signal from said feedback delay path, said delay-locked loop further including a phase detector configured to adapt a sampling rate responsive to said loop delay.

Claim 30

An electronic system, comprising: a processor; at least one of an input device and an output device operably coupled to said processor; and a memory device operably coupled to said processor, said memory device including: a memory array with an output driver coupled thereto; and a delay-locked loop operably coupled between said output driver and configured to couple with an external clock signal, said delay-locked loop including forward and feedback delay paths, said delay-locked loop configured to switchably couple a test signal into said forward delay path and calculate a loop delay from receipt of said test signal from said feedback delay path, said delay-locked loop further including a phase detector configured to adapt a sampling rate responsive to said loop delay.

Claim 31

The electronic system, as recited in claim 25 , wherein said feedback delay path comprises a delay model of said output driver of said memory device.

Claim 32

The electronic system, as recited in claim 26 , wherein said feedback delay path further comprises a second delay model configured to model delay of an input portion of said forward delay path.

Claim 33

The electronic system, as recited in claim 25 , wherein said forward delay path comprises an adjustable delay line configured to adjust delay of said external clock signal through said forward delay path.

Claim 34

The electronic system, as recited in claim 28 , wherein said adjustable delay line is configured with a first delay path for inserting a delay during an initialization mode of said phase detector and a second delay path for inserting a delay during an operational mode of said delay-locked loop.

Claim 35

The electronic system, as recited in claim 29 , wherein said first delay path is configured as a synchronous mirror delay.

Claim 36

A signal locking method, comprising: inputting an external clock signal into a forward loop path; initializing a phase detector with an approximate forward loop delay responsive to said external clock signal passing through said forward loop path and a feedback loop path; temporarily switching a test clock signal into said forward loop path; timing said test clock signal around said forward loop path and said feedback loop path; and configuring said phase detector responsive to a delay of said test clock signal traversing said forward loop path and said feedback loop path.

Claim 37

A signal locking method, comprising: inputting an external clock signal into a forward loop path; initializing a phase detector with an approximate forward loop delay responsive to said external clock signal passing through said forward loop path and a feedback loop path; temporarily switching a test clock signal into said forward loop path; timing said test clock signal around said forward loop path and said feedback loop path; and configuring said phase detector responsive to a delay of said test clock signal traversing said forward loop path and said feedback loop path.

Claim 38

The method, as recited in claim 31 , wherein configuring said phase detector comprises updating a sampling rate of said phase detector based upon said delay of said test clock signal around said forward loop path and said feedback loop path.

Claim 39

The method, as recited in claim 31 , wherein temporarily switching a test clock signal comprises: switching said external clock signal out of said forward loop path; delaying while said external clock signal completely traverses said forward loop path and said feedback loop path; and inputting said test clock signal into said forward loop path.

Claim 40

The method, as recited in claim 31 , wherein initializing a phase detector comprises: configuring a delay line to converge on an approximate forward loop delay; and updating said approximate forward loop delay in response to a phase difference of said external clock signal and a feedback signal from said feedback loop path.

Claim 41

The method, as recited in claim 34 , wherein said delay line is a synchronous mirror delay type.

Claim 42

A DLL loop delay measurement method, comprising: inputting an external clock signal into a forward loop path; initializing a phase detector with an approximate forward loop delay responsive to said external clock signal passing through said forward loop path and a feedback loop path; temporarily switching a test clock signal into said forward loop path; timing said test clock signal around said forward loop path and said feedback loop path; and configuring said phase detector responsive to a delay of said test clock signal traversing said forward loop path and said feedback loop path.

Claim 43

A DLL loop delay measurement method, comprising: inputting an external clock signal into a forward loop path; initializing a phase detector with an approximate forward loop delay responsive to said external clock signal passing through said forward loop path and a feedback loop path; temporarily switching a test clock signal into said forward loop path; timing said test clock signal around said forward loop path and said feedback loop path; and configuring said phase detector responsive to a delay of said test clock signal traversing said forward loop path and said feedback loop path.

Claim 44

The method, as recited in claim 36 , wherein configuring said phase detector comprises updating a sampling rate of said phase detector based upon said delay of said test clock signal around said forward loop path and said feedback loop path.

Claim 45

The method, as recited in claim 36 , wherein temporarily switching a test clock signal comprises: switching said external clock signal out of said forward loop path; delaying while said external clock signal completely traverses said forward loop path and said feedback loop path; and inputting said test clock signal into said forward loop path.

Claim 46

The method, as recited in claim 36 , wherein said test clock signal is a detectable derivative of said external clock signal.