Method and apparatus for correcting a clock duty cycle in a clock distribution network

Claim 3

The apparatus of claim 1 wherein the duty cycle correction circuit includes a feedback path between an input and an output of the duty cycle correction circuit, the feedback path to control a delay of a circuit path in the duty cycle correction circuit to correct the duty cycle.

Claim 4

The apparatus of claim 2 wherein the duty cycle of the duty-cycle-corrected output clock signal is substantially equal to 50%.

Claim 5

The apparatus of claim 2 further including: a sense amplifier in the feedback path, the sense amplifier having a threshold substantially equal to one half of a supply voltage (Vcc) to be coupled to the duty cycle correction circuit.

Claim 6

The apparatus of claim 4 further including: a reset path between the input of the duty cycle correction circuit and the output of the duty cycle correction circuit, the reset path to control a width of the output clock signal.

Claim 7

The apparatus of claim 5 wherein the reset path and the feedback path is coupled to control a variable delay element.

Claim 8

The apparatus of claim 1 further including a smart buffer circuit coupled to an output of the duty cycle correction circuit, the smart buffer circuit to provide for proper operation of the duty cycle correction circuit over a range of loads to be coupled to the duty cycle correction circuit.

Claim 9

The apparatus of claim 7 wherein the smart buffer circuit is to match a delay of the duty-cycle-corrected output clock signal to a delay of a reference signal independent of a load coupled to the duty cycle correction circuit over the range of loads, the smart buffer circuit to adjust the delay of the duty-cycle-corrected output clock signal by adjusting the drive strength of an output driver in the duty cycle correction circuit.

Claim 10

The apparatus of claim 8 wherein the smart buffer includes a first phase detector to detect a difference in delay between one of a rising or falling edge of the duty-cycle-corrected output clock signal and a corresponding edge of the reference signal, the first phase detector to provide a first reference control signal at a first output, the first reference control signal to control a delay of a first delay element in the duty cycle correction circuit to adjust the drive strength of the driver for a first value of an input signal to the duty cycle correction circuit.

Claim 11

The apparatus of claim 9 wherein the smart buffer circuit further includes a second phase detector to detect a difference in d lay between a remaining one of a rising or falling edge of the duty-cycle-corrected output clock signal and a corresponding edge of the reference signal, the second phase detector to provide a second reference control signal at a second output, the second reference control signal to control a delay of a second delay element in the duty cycle correction circuit to adjust the drive strength of the output driver for a second value of the input signal to the duty cycle correction circuit.

Claim 12

The apparatus of claim 1 wherein the duty cycle correction circuit is to generate a reference voltage signal, a voltage of the reference voltage signal to vary in response to a change in frequency of the distributed clock signal, the apparatus further comprising, a clock generation circuit to receive the reference voltage signal and to provide an output clock signal, the clock generation circuit to very the delay of the output clock signal in response to a variation in voltage of the reference voltage signal.

Claim 13

The apparatus of claim 11 wherein the clock generation circuit is to provide multiple output clock signals, each of the multiple output clock signals to vary in response to a variation in the voltage of the reference voltage signal.

Claim 14

A clock distribution network comprising: clock generation circuitry at a first location to generate a global clock signal; clock distribution circuitry to distribute the global clock signal on an integrated circuit chip from the clock generation circuitry to a receiving point at a second, different location on the integrated circuit chip; and a duty cycle correction circuit at the receiving point to correct the duty cycle of the distributed global clock signal received via the clock distribution circuitry, wherein a frequency multiplying circuit is further coupled to the duty cycle correction circuit, the duty cycle correction circuit and the frequency multiplying circuit to work cooperatively to provide a multiplied, duty-cycle-corrected cutout clock signal.

Claim 15

A clock distribution network comprising: clock generation circuitry at a first location to generate a global clock signal; clock distribution circuitry to distribute the global clock signal on an integrated circuit chip from the clock generation circuitry to a receiving point at a second, different location on the integrated circuit chip; and a duty cycle correction circuit at the receiving point to correct the duty cycle of the distributed global clock signal received via the clock distribution circuitry, wherein a frequency multiplying circuit is further coupled to the duty cycle correction circuit, the duty cycle correction circuit and the frequency multiplying circuit to work cooperatively to provide a multiplied, duty-cycle-corrected cutout clock signal.

Claim 16

The clock distribution network of claim 13 wherein the clock distribution circuitry is further to distribute the global clock signal from the clock generation circuitry to a plurality of receiving points and wherein each of the plurality of receiving points is coupled to an associated duty cycle correction circuit.

Claim 17

The clock distribution network of claim 13 wherein the duty cycle correction circuit includes a feedback path to control a delay of the output clock signal.

Claim 18

The clock distribution network of claim 15 wherein a signal communicated via the feedback path in the duty cycle correction circuit is to control at least one variable delay element in the duty cycle correction circuit.

Claim 19

The clock distribution network of claim 13 wherein the output clock signal has a substantially 50% duty cycle.