US6587411B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal processing circuit having a voltage controlled oscillator capable of continuously changing the center frequency in accordance with a control voltage
Assignee: Toshiba Corp
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Filing: 1997-01-14
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Granted: 2003-07-01
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Expires: 2017-01-14
Abstract
Abstract A laser beam is irradiated from a pickup head on a disk. Light reflected by the disk is detected by the pickup head. The data is binarized by a data slice circuit, and a synchronizing clock and a synchronizing signal are extracted by a PLL and synchronizing signal separation circuit. The center frequency of the voltage controlled oscillator of the PLL and synchronizing signal separation circuit continuously changes according to a control voltage. A disk motor control circuit continuously changes the rotation speed of the disk in accordance with a control instruction from a system controller. The disk rotates at the highest rotation speed at which a data read operation is normally performed. The characteristics of the voltage controlled oscillator change in correspondence with the rotation speed of the disk.
Inventors
- 👤 Yasuhiro Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:14
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; G11B20/10222; G11B20/1024; G11B19/00; G11B19/20; G11B19/28; G11B19/2009; G11B19/26; G11B20/10527; G11B7/00; G11B7/004; G11B7/005; G11B20/18; G11B20/1816; G11B2020/1823
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
93 words
A signal processing circuit comprising: a data slice circuit which binarizes data read from a disk and generates binarized data; a PLL circuit receiving the binarized data and having a voltage controlled oscillator which controls an output frequency in accordance with a first control voltage associated with the binarized data, and which is capable of controlling a center frequency in accordance with a second control voltage as an analog signal; and wherein the output frequency is changed by the first control voltage and the center frequency is changed by the second control voltage.
Claim 2
Dependent Claim
93 words
A signal processing circuit comprising: a data slice circuit which binarizes data read from a disk and generates binarized data; a PLL circuit receiving the binarized data and having a voltage controlled oscillator which controls an output frequency in accordance with a first control voltage associated with the binarized data, and which is capable of controlling a center frequency in accordance with a second control voltage as an analog signal; and wherein the output frequency is changed by the first control voltage and the center frequency is changed by the second control voltage.
Claim 3
Dependent Claim
28 words
A signal processing circuit according to claim 1 , further comprising a disk motor control circuit which rotates the disk and changing a rotation speed of the disk.
Claim 4
Dependent Claim
48 words
A signal processing circuit according to claim 1 , further comprising memory means for storing the binarized data, and error correction means, operated on the basis of the output frequency, for performing error correction processing of the binarized data, and generating a correction flag and a corresponding flag.
Claim 5
Dependent Claim
49 words
A signal processing circuit according to claim 1 , wherein the PLL/circuit includes a phase comparator which compares phases of the binarized data and the output frequency and which outputs the first control voltage, and a detector which detects data associated with a predetermined frequency from the binarized data.
Claim 6
Dependent Claim
19 words
A signal processing circuit according to claim 1 , wherein the center frequency changes coincidently with the output frequency.
Claim 7
Dependent Claim
108 words
A read apparatus comprising: a disk motor control circuit which rotates a disk; a pickup circuit which reads data from the disk; a data slice circuit which binarizes the read data and generates binarized data; a PLL circuit receiving the binarized data and having a voltage controlled oscillator which controls an output frequency in accordance with a first control voltage associated with the binarized data, and which is capable of controlling a center frequency in accordance with a second control voltage as an analog signal; and wherein when the output frequency is changed by the first control voltage, the center frequency is changed by the second control voltage.
Claim 8
Dependent Claim
108 words
A read apparatus comprising: a disk motor control circuit which rotates a disk; a pickup circuit which reads data from the disk; a data slice circuit which binarizes the read data and generates binarized data; a PLL circuit receiving the binarized data and having a voltage controlled oscillator which controls an output frequency in accordance with a first control voltage associated with the binarized data, and which is capable of controlling a center frequency in accordance with a second control voltage as an analog signal; and wherein when the output frequency is changed by the first control voltage, the center frequency is changed by the second control voltage.
Claim 9
Dependent Claim
47 words
A read apparatus according to claim 6 , further comprising memory means for storing the binarized data, and error correction means, operated on the basis of the output frequency, for performing error correction processing of the binarized data, and generating a correction flag and a compensation flag.
Claim 10
Dependent Claim
48 words
A read apparatus according to claim 6 , wherein the PLL/circuit includes a phase comparator which compares phase of the binarized data and the output frequency, and which outputs the first control voltage, and a detector which detects data associated with a predetermined frequency from the binarized data.
Claim 11
Dependent Claim
18 words
A read apparatus according to claim 6 , wherein the center frequency changes coincidently with the output frequency.
Claim 12
Dependent Claim
28 words
A signal processing circuit according to claim 1 , wherein when the output frequency is changed, the center frequency is changed to be closer to the output frequency.
Claim 13
Dependent Claim
35 words
A signal processing circuit according to claim 1 , wherein when the output frequency is changed, the center frequency is changed so that a difference between the center frequency and the output frequency is lessened.
Claim 14
Dependent Claim
27 words
A read apparatus according to claim 6 , wherein when the output frequency is changed, the center frequency is changed to be closer to the output frequency.
Claim 15
Dependent Claim
34 words
A read apparatus according to claim 6 , wherein when the output frequency is changed, the center frequency is changed so that a difference between the center frequency and the output frequency is lessened.
Claim 16
Dependent Claim
116 words
A signal processing circuit comprising: a data slice circuit which binarizes data read from a disk and generates binarized data; a controller for generating a control instruction as a digital signal; a PLL circuit receiving the binarized data and having a voltage controlled oscillator which controls an output frequency in accordance with a first control voltage associated with the binarized data, and which is capable of controlling a center frequency in accordance with a second control voltage as an analog signal; a converter for converting the control instruction into the second control voltage; and wherein the output frequency is changed by the first control voltage and the center frequency is changed by the second control voltage.
Claim 17
Dependent Claim
116 words
A signal processing circuit comprising: a data slice circuit which binarizes data read from a disk and generates binarized data; a controller for generating a control instruction as a digital signal; a PLL circuit receiving the binarized data and having a voltage controlled oscillator which controls an output frequency in accordance with a first control voltage associated with the binarized data, and which is capable of controlling a center frequency in accordance with a second control voltage as an analog signal; a converter for converting the control instruction into the second control voltage; and wherein the output frequency is changed by the first control voltage and the center frequency is changed by the second control voltage.
Claim 18
Dependent Claim
23 words
A signal processing circuit according to claim 14 , further comprising a converter for converting the control instruction into the second control voltage.
Claim 19
Dependent Claim
30 words
A signal processing circuit according to claim 15 , wherein the converter is connected between the PLL circuit and an interface circuit, and the controller connected to the interface circuit.
Claim 20
Dependent Claim
28 words
A signal processing circuit according to claim 14 , further comprising a disk motor control circuit which rotates the disk and changing a rotation speed of the disk.
Claim 21
Dependent Claim
48 words
A signal processing circuit according to claim 14 , further comprising memory means for storing the binarized data, and error correction means, operated on the basis of the output frequency, for performing error correction processing of the binarized data, and generating a correction flag and a corresponding flag.
Claim 22
Dependent Claim
62 words
A signal processing circuit according to claim 14 , wherein the PLL circuit includes a first control voltage generator for generating the first control voltage, and the first control voltage generator includes a phase comparator which compares phases of the binarized data and the output frequency, and a frequency detector which detects data associated with a predetermined frequency from the binarized data.
Claim 23
Dependent Claim
19 words
A signal processing circuit according to claim 14 , wherein the center frequency changes coincidently with the output frequency.
Claim 24
Dependent Claim
28 words
A signal processing circuit according to claim 14 , wherein when the output frequency is changed, the center frequency is changed to be closer to the output frequency.
Claim 25
Dependent Claim
35 words
A signal processing circuit according to claim 14 , wherein when the output frequency is changed, the center frequency is changed so that a difference between the center frequency and the output frequency is lessened.
Claim 26
Dependent Claim
131 words
A read apparatus comprising: a disk motor control circuit which rotates a disk; a pickup circuit which reads data from the disk; a data slice circuit which binarizes the read data and generates binarized data; a controller for generating a control instruction as a digital signal; a PLL circuit receiving the binarized data and having a voltage controlled oscillator which controls a output frequency in accordance with a first control voltage associated with the binarized data, and which is capable of controlling a center frequency in accordance with a second control voltage as an analog signal; a converter for converting the control instruction into the second control voltage; and wherein the output frequency is changed by the first control voltage and the center frequency is changed by the second control voltage.
Claim 27
Dependent Claim
131 words
A read apparatus comprising: a disk motor control circuit which rotates a disk; a pickup circuit which reads data from the disk; a data slice circuit which binarizes the read data and generates binarized data; a controller for generating a control instruction as a digital signal; a PLL circuit receiving the binarized data and having a voltage controlled oscillator which controls a output frequency in accordance with a first control voltage associated with the binarized data, and which is capable of controlling a center frequency in accordance with a second control voltage as an analog signal; a converter for converting the control instruction into the second control voltage; and wherein the output frequency is changed by the first control voltage and the center frequency is changed by the second control voltage.
Claim 28
Dependent Claim
22 words
A read apparatus according to claim 23 , further comprising a converter for converting the control instruction into the second control voltage.
Claim 29
Dependent Claim
30 words
A read apparatus according to claim 24 , wherein the converter is connected between the PLL circuit and an interface circuit, and the controller is connected to the interface circuit.
Claim 30
Dependent Claim
47 words
A read apparatus according to claim 23 , further comprising memory means for storing the binarized data, and error correction means, operated on the basis of the output frequency, for performing error correction processing of the binarized data, and generating a correction flag and a corresponding flag.
Claim 31
Dependent Claim
61 words
A read apparatus according to claim 23 , wherein the PLL circuit includes a first control voltage generator for generating the first control voltage, and the first control voltage generator includes a phase comparator which compares phases of the binarized data and the output frequency, and a frequency detector which detects data associated with a predetermined frequency from the binarized data.
Claim 32
Dependent Claim
18 words
A read apparatus according to claim 23 , wherein the center frequency changes coincidently with the output frequency.
Claim 33
Dependent Claim
27 words
A read apparatus according to claim 23 , wherein when the output frequency is changed, the center frequency is changed to be closer to the output frequency.
Claim 34
Dependent Claim
34 words
A read apparatus according to claim 23 , wherein when the output frequency is changed, the center frequency is changed so that a difference between the center frequency and the output frequency is lessened.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-06-30 | 2006-12-30 | 2007-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-06-30 | 2010-12-30 | 2011-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-06-30 | 2014-12-30 | 2015-07-01 | $7700.00 | Window Closed / Lapsed |