US5019785A — Frequency synthesizing device

Claim 1

Independent Claim 338 words

A frequency synthesizing device for the generation of signals covering various frequency channels, comprising first and second reference frequency generators (RG1, RG2), an offset stage having a first input coupled to an output of said second reference frequency generator, a second input coupled to a source that provides an offset reference signal (s OR ) and an output which provides an output signal (s OS ) and a phase-locked loop (PLL), which operates as a tracking filter having a known bandwidth, having a first input coupled to an output of said first reference frequency generator, a second input coupled to the output of said offset stage and an output which provides an output signal (s A ), wherein: said first and second reference frequency generators output first and second signals (s RG1 ) and (s RG2 ), respectively, whose respective frequencies (f RG1 ) and (f RG2 ) are selectable to be equal to a fraction of a standard frequency (f BZ ); the frequency (f OS ) of the output signal (s OS ) of said offset stage takes on one of (a) the value of a predetermined frequency (f OR ) of the offset reference signal (s OR ) and (b) the value of a frequency (f OR +f RG2 ) of a sum or difference signal formed by combining the offset reference and second reference frequency generator signals (s OR ) and (s RG2 ); at the output of a voltage-controlled oscillator (VCO) in the phase-locked loop (PLL), there is generated the output signal (s A ) at a frequency (fs A ) formed by the addition of the frequency (f RG1 ) and (f OS ) of the first reference frequency generator and offset stage signals (s RG1 ) and (s OS ), respectively; and wherein all the frequencies output by said first and second reference frequency generators and by said offset stage are selectable and combinable with one another such that the resulting sidebands always lie outside the bandwidth of the phase-locked loop.

Claim 2

Dependent Claim 338 words

A frequency synthesizing device for the generation of signals covering various frequency channels, comprising first and second reference frequency generators (RG1, RG2), an offset stage having a first input coupled to an output of said second reference frequency generator, a second input coupled to a source that provides an offset reference signal (s OR ) and an output which provides an output signal (s OS ) and a phase-locked loop (PLL), which operates as a tracking filter having a known bandwidth, having a first input coupled to an output of said first reference frequency generator, a second input coupled to the output of said offset stage and an output which provides an output signal (s A ), wherein: said first and second reference frequency generators output first and second signals (s RG1 ) and (s RG2 ), respectively, whose respective frequencies (f RG1 ) and (f RG2 ) are selectable to be equal to a fraction of a standard frequency (f BZ ); the frequency (f OS ) of the output signal (s OS ) of said offset stage takes on one of (a) the value of a predetermined frequency (f OR ) of the offset reference signal (s OR ) and (b) the value of a frequency (f OR +f RG2 ) of a sum or difference signal formed by combining the offset reference and second reference frequency generator signals (s OR ) and (s RG2 ); at the output of a voltage-controlled oscillator (VCO) in the phase-locked loop (PLL), there is generated the output signal (s A ) at a frequency (fs A ) formed by the addition of the frequency (f RG1 ) and (f OS ) of the first reference frequency generator and offset stage signals (s RG1 ) and (s OS ), respectively; and wherein all the frequencies output by said first and second reference frequency generators and by said offset stage are selectable and combinable with one another such that the resulting sidebands always lie outside the bandwidth of the phase-locked loop.

Claim 3

Dependent Claim 67 words

A frequency synthesizing device according to claim 1, wherein all the frequencies (f RG1 ) and (f RG2 ) provided by the reference frequency generators correspond to a multiple of the lowest frequency (f RG1min ) generated by the reference frequency generator and that the value of the frequency (f RG1min ) is larger than half the bandwidth of the tracking filter (f RG1min > 1/2 BTF).

Claim 4

Dependent Claim 33 words

A frequency synthesizing device according to claim 2, wherein all the frequencies (f RG2 ) correspond to a multiple of the highest frequency (f RG1max ) generated by the reference frequency generator (RG1).

Claim 5

Dependent Claim 74 words

A frequency synthesizing device according to claim 1, wherein the phase-locked loop includes a phase detector and the signals (s A ) and (s OS ) are fed to a mixer stage (M1) in the phase-locked loop (PLL), at whose output there is formed a signal (s M1 ) with the frequency (fs A -f OS ), whose phase is compared in the phase detector with the phase of the signal (s RG1 ).

Claim 6

Dependent Claim 74 words

A frequency synthesizing device according to claim 2, wherein the phase-locked loop includes a phase detector and the signals (s A ) and (s OS ) are fed to a mixer stage (M1) in the phase-locked loop (PLL), at whose output there is formed a signal (s M1 ) with the frequency (fs A -f OS ), whose phase is compared in the phase detector with the phase of the signal (s RG1 )

Claim 7

Dependent Claim 74 words

A frequency synthesizing device according to claim 3, wherein the phase-locked loop includes a phase detector and the signals (s A ) and (s OS ) are fed to a mixer stage (M1) in the phase-locked loop (PLL), at whose output there is formed a signal (s M1 ) with the frequency (fs A -f OS ), whose phase is compared in the phase detector with the phase of the signal (s RG1 ).

Claim 8

Dependent Claim 89 words

A frequency synthesizing device according to claim 4, wherein at least one of the following conditions is met: the offset reference frequency (f OR ) satisfies the condition f OR =k×f BZ (k<1 or k>1), k being an integer; the offset reference frequency (f OR ) is generated by selection from one of a number of wave generators with a stable frequency; and the offset reference frequency (f OR ) is at least approximately variable in accordance with half the channel interval of the output frequencies (fs A ).

Claim 9

Dependent Claim 21 words

A frequency synthesizing device according to claim 1, wherein the signal (s A ) can be fed to a frequency multiplier.

Claim 10

Dependent Claim 62 words

Frequency synthesizing device according to claim 1, wherein it is interconnected with other similar frequency synthesizing devices such that the signals (s A ) of the individual devices are switchable by way of one of a switch and a multiplexer to a user and that the devices in this case cover frequency channels that are identical or, at least in part, different.

Claim 11

Dependent Claim 41 words

A frequency synthesizing device according to claim 1, wherein the input of the voltage-controlled oscillator (VCO) can be switched over to the output of a digital/analog converter, by way of the frequency (fs A ) can be set by digital means.

Claim 12

Dependent Claim 34 words

A frequency synthesizing device according to claim 4, wherein the output signal (s M1 ) of the mixer stage is fed by way of a frequency divider to the input of the phase detector.

Claim 13

Dependent Claim 291 words

A frequency synthesizing device for the generation of signals covering various frequency channels, including first and second reference frequency generators, an offset stage providing an output signal (s os ) and a phase-locked loop being operated as a tracking filter and having a voltage-controlled oscillator and first and second inputs, wherein: the first and second reference frequency generators (RG1, RG2) generate respective first and second signals (s RG1 ) and (s RG2 ) which are applied to the first input of the phase-locked loop (PLL) and to the offset stage (OS) respectively, and whose respective frequencies (f RG1 ,RG2) are selectable to be equal to a fraction of a standard frequency (f BZ ); the frequency (f OS ) of the output signal (s OS ) of the offset stage (OS) is applied to the second input of the phase-locked loop (PLL) and takes on one of (a) the value of a predetermined frequency (f OR ) of an offset reference signal (s OR ) and (b) the value of a frequency (f OR +/-f RG2 ) of a sum or difference signal formed by combining signals (s OR ) and (s RG2 ); at the output of the voltage-controlled oscillator (VCO) in the phase controlled loop (PLL) there is generated the output signal (s A ) of the frequency synthesizing device at a frequency (fs A ) formed by the addition of the frequency (f RG1 ) and (f OS ) of the signals (s RG1 ) and (s OS ), respectively; and wherein all the frequencies of the reference frequency generators (RG1, RG2) and the offset stage (OS) are selectable and combinable with one another such that the resulting sidebands always lie outside the bandwidth of the tracking filter.

Claim 14

Dependent Claim 291 words

A frequency synthesizing device for the generation of signals covering various frequency channels, including first and second reference frequency generators, an offset stage providing an output signal (s os ) and a phase-locked loop being operated as a tracking filter and having a voltage-controlled oscillator and first and second inputs, wherein: the first and second reference frequency generators (RG1, RG2) generate respective first and second signals (s RG1 ) and (s RG2 ) which are applied to the first input of the phase-locked loop (PLL) and to the offset stage (OS) respectively, and whose respective frequencies (f RG1 ,RG2) are selectable to be equal to a fraction of a standard frequency (f BZ ); the frequency (f OS ) of the output signal (s OS ) of the offset stage (OS) is applied to the second input of the phase-locked loop (PLL) and takes on one of (a) the value of a predetermined frequency (f OR ) of an offset reference signal (s OR ) and (b) the value of a frequency (f OR +/-f RG2 ) of a sum or difference signal formed by combining signals (s OR ) and (s RG2 ); at the output of the voltage-controlled oscillator (VCO) in the phase controlled loop (PLL) there is generated the output signal (s A ) of the frequency synthesizing device at a frequency (fs A ) formed by the addition of the frequency (f RG1 ) and (f OS ) of the signals (s RG1 ) and (s OS ), respectively; and wherein all the frequencies of the reference frequency generators (RG1, RG2) and the offset stage (OS) are selectable and combinable with one another such that the resulting sidebands always lie outside the bandwidth of the tracking filter.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-05-27	1994-11-26	1995-05-28	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-05-27	1998-11-26	1999-05-28	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-05-27	2002-11-26	2003-05-28	$7700.00	Window Closed / Lapsed

Frequency synthesizing device

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