US5579184A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Playback clock signal generating circuit which uses a first and second phase lock loop
Assignee: Vista Peak Ventures LLC
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Filing: 1994-06-14
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Granted: 1996-11-26
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Expires: 2014-06-14
Abstract
Abstract A playback clock signal generating circuit has first and second phase-locked loops PLLs. The first PLL has a voltage-controlled oscillator VCO controllable by an output signal from a low-pass filter for outputting a signal, a variable frequency divider for varying a frequency-dividing number depending on head position information and frequency-dividing the signal from the VCO with the varied frequency-dividing number, a reference oscillator for outputting a reference signal having a frequency equal to a predetermined frequency step, a phase comparator for detecting the phase or frequency difference between an output signal from the variable frequency divider and the reference signal, and outputting the detected phase or frequency difference to the low-pass filter. The second PLL has a VCO controllable by a low-pass filter for outputting a signal, a mixer for frequency-converting the signal from the VCO with the signal from the VCO of the first PLL to output a playback clock signal, and a phase comparator for detecting the phase difference between a reproduced data signal and the playback clock signal and outputting the detected phase difference to the low-pass filter.
Inventors
- 👤 Shuichi Nakanishi
- 👤 Shinichi Kitahara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:25
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; H; H03; H03L; H03L7/00; H03L7/06; H03L7/07; H03L7/08; H03L7/085; H03L7/089; G11B20/12; G11B20/1217; G11B20/1258
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
241 words
A playback clock signal generating circuit of a disk recording and reproducing apparatus for generating a playback clock signal in accordance with a head position information and reproduced data signal, comprising: a first phase-locked loop for outputting a first signal having a variable frequency in a predetermined frequency step depending on the head position information, wherein said first phase-locked loop includes a first voltage-controlled oscillator for outputting said first signal, a variable frequency divider for varying a frequency-dividing number depending on said head position information and frequency-dividing said first signal with the varied frequency-dividing number, a reference oscillator for outputting a reference signal having a frequency equal to said predetermined frequency step, a first phase comparator responsive to an output signal from said variable frequency divider and said reference signal, for detecting the phase difference therebetween, and a first low-pass filter connected between said first phase comparator and said first voltage-controlled oscillator; and a second phase-locked loop for outputting a playback clock signal in response to the reproduced data signal and said first signal wherein said second phase-locked loop includes a second voltage-controlled oscillator for outputting a second signal, a mixer for frequency-converting said second signal with said first signal to output said playback clock signal, a second phase comparator responsive to the reproduced data signal and the playback clock signal outputted from said mixer, and a second low-pass filter connected between said second phase comparator and said second voltage-controlled oscillator.
Claim 2
Dependent Claim
241 words
A playback clock signal generating circuit of a disk recording and reproducing apparatus for generating a playback clock signal in accordance with a head position information and reproduced data signal, comprising: a first phase-locked loop for outputting a first signal having a variable frequency in a predetermined frequency step depending on the head position information, wherein said first phase-locked loop includes a first voltage-controlled oscillator for outputting said first signal, a variable frequency divider for varying a frequency-dividing number depending on said head position information and frequency-dividing said first signal with the varied frequency-dividing number, a reference oscillator for outputting a reference signal having a frequency equal to said predetermined frequency step, a first phase comparator responsive to an output signal from said variable frequency divider and said reference signal, for detecting the phase difference therebetween, and a first low-pass filter connected between said first phase comparator and said first voltage-controlled oscillator; and a second phase-locked loop for outputting a playback clock signal in response to the reproduced data signal and said first signal wherein said second phase-locked loop includes a second voltage-controlled oscillator for outputting a second signal, a mixer for frequency-converting said second signal with said first signal to output said playback clock signal, a second phase comparator responsive to the reproduced data signal and the playback clock signal outputted from said mixer, and a second low-pass filter connected between said second phase comparator and said second voltage-controlled oscillator.
Claim 3
Dependent Claim
91 words
A playback clock signal generating circuit according to claim 1, wherein said second phase-locked loop further includes pulse generating means for generating pulses at a frequency which is the same as an output signal from said second phase comparator, said pulses each having a duration in a predetermined proportion with respect to the period of the playback clock signal, said second low-pass filter comprising means for filtering a signal representative of the difference between the output signal from said second phase comparator and an output signal from said pulse generating means.
Claim 4
Dependent Claim
33 words
A playback clock signal generating circuit according to claim 1, wherein said second phase-locked loop has a range of synchronizing frequencies which is established depending on an error of said head position information.
Claim 5
Dependent Claim
56 words
A playback clock signal generating circuit according to claim 3, further comprising means for detecting the frequency of the output signal from said second voltage-controlled oscillator, and a control circuit for varying the frequency of the output signal from said first phase-locked loop depending on the frequency of the output signal from said second voltage-controlled oscillator.
Claim 6
Dependent Claim
67 words
A playback clock signal generating circuit according to claim 4, further comprising a voltage comparator for comparing a control voltage of said second voltage-controlled oscillator and a reference voltage, and producing an output signal representing the result of comparison, and a control circuit responsive to said output signal from said voltage comparator as a frequency-dividing-ratio changing signal for varying a frequency-dividing ratio of said variable frequency divider.
Claim 7
Dependent Claim
51 words
A playback clock signal generating circuit according to claim 4, further comprising a counter for measuring the period of said second signal outputted from said second voltage-controlled oscillator and outputting a count indicative of the measured period as a frequency-dividing-ratio changing signal for varying a frequency-dividing-ratio of said variable frequency divider.
Claim 8
Dependent Claim
214 words
A playback clock signal generating circuit for generating a playback clock signal from a data signal and a head position information, said playback clock signal being in synchronization with said data signal, said data signal being read and reproduced by a head from data written on a disk at a frequency selected from a plurality of frequencies which varies stepwise, said head position information being indicative of a radial position of the head which moves radially over the disk during disk read/write operations as the disk is being rotated at a constant speed, said playback clock signal generating circuit comprising: a first phase-locked loop for outputting a first signal having a frequency variable in a predetermined frequency step depending on the head position information; and a second phase-locked loop for outputting a playback clock signal in response to the reproduced data signal and said first signal, wherein said second phase-locked loop includes a second voltage-controlled oscillator for outputting a second signal; a mixer for frequency converting said second signal with said first signal to output said playback clock signal; a second phase comparator responsive to the reproduced data signal and the playback clock signal outputted from said mixer; and a second low-pass filter connected between said second phase comparator and said second voltage-controlled oscillator.
Claim 9
Dependent Claim
214 words
A playback clock signal generating circuit for generating a playback clock signal from a data signal and a head position information, said playback clock signal being in synchronization with said data signal, said data signal being read and reproduced by a head from data written on a disk at a frequency selected from a plurality of frequencies which varies stepwise, said head position information being indicative of a radial position of the head which moves radially over the disk during disk read/write operations as the disk is being rotated at a constant speed, said playback clock signal generating circuit comprising: a first phase-locked loop for outputting a first signal having a frequency variable in a predetermined frequency step depending on the head position information; and a second phase-locked loop for outputting a playback clock signal in response to the reproduced data signal and said first signal, wherein said second phase-locked loop includes a second voltage-controlled oscillator for outputting a second signal; a mixer for frequency converting said second signal with said first signal to output said playback clock signal; a second phase comparator responsive to the reproduced data signal and the playback clock signal outputted from said mixer; and a second low-pass filter connected between said second phase comparator and said second voltage-controlled oscillator.
Claim 10
Dependent Claim
107 words
A playback clock signal generating circuit according to claim 7, wherein said first phase-locked loop comprises: a first voltage-controlled oscillator for outputting said first signal; a variable frequency divider for varying a frequency-dividing number depending on said head position information and frequency-dividing said first signal with the varied frequency-dividing number; a reference oscillator for outputting a reference signal having a frequency equal to said predetermined frequency step; a first phase comparator responsive to an output signal from said variable frequency divider and said reference signal, for detecting the phase difference therebetween; and a first low-pass filter connected between said first phase comparator and said first voltage-controlled oscillator.
Claim 11
Dependent Claim
98 words
A playback clock signal generating circuit according to claim 7, wherein said first phase-locked comprises: frequency-converting means for shifting the frequency of said first signal by a predetermined frequency; a variable frequency divider for varying a frequency-dividing number depending on said head position information and frequency-dividing an output signal from said frequency-converting means with the varied frequency-dividing number; a first phase comparator responsive to an output signal from said variable frequency divider and said reference signal, for detecting the phase difference therebetween; and a first low-pass filter connected between said first phase comparator and said first voltage-controlled oscillator.
Claim 12
Dependent Claim
91 words
A playback clock signal generating circuit according to claim 7, wherein said second phase-locked loop further includes pulse generating means for generating pulses at a frequency which is the same as an output signal from said second phase comparator, said pulses each having a duration in a predetermined proportion with respect to the period of the playback clock signal, said second low-pass filter comprising means for filtering a signal representative of the difference between the output signal from said second phase comparator and an output signal from said pulse generating means.
Claim 13
Dependent Claim
33 words
A playback clock signal generating circuit according to claim 7, wherein said second phase-locked loop has a range of synchronizing frequencies which is established depending on an error of said head position information.
Claim 14
Dependent Claim
56 words
A playback clock signal generating circuit according to claim 11, further comprising means for detecting the frequency of the output signal from said second voltage-controlled oscillator, and a control circuit for varying the frequency of the output signal from said first phase-locked loop depending on the frequency of the output signal from said second voltage-controlled oscillator.
Claim 15
Dependent Claim
66 words
A playback clock signal generating circuit according to claim 12, further comprising a voltage comparator for comparing a control voltage of said second voltage-controlled oscillator and a reference voltage, and producing an output signal representing the result of comparison, and a control circuit responsive to said output signal from said voltage comparator as a frequency-dividing-ratio changing signal for varying a frequency-dividing-ratio of said variable frequency divider.
Claim 16
Dependent Claim
52 words
A playback clock signal generating circuit according to claim 12, further comprising a counter for measuring the period of said second signal outputted from said second voltage-controlled oscillator and outputting a count indicative of the measured period as a frequency-dividing-ratio changing signal for varying a frequency-dividing ratio of said variable frequency divider.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-26 | 2000-05-27 | 2000-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-26 | 2004-05-27 | 2004-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-26 | 2008-05-27 | 2008-11-26 | $7700.00 | Window Closed / Lapsed |