US5638014A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock pulse generator
Assignee: Renesas Electronics Corp
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Filing: 1995-11-08
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Granted: 1997-06-10
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Expires: 2015-11-08
Abstract
Abstract A simply structured clock pulse generator operating stably in a wide range of frequencies in response to a timing signal fed from outside a semiconductor integrated circuit. A first frequency signal fed from the external terminal of the semiconductor integrated circuit and a second frequency signal generated within the semiconductor integrated circuit are input to a phase comparator. The output signal of the phase comparator is smoothed by a low-pass filter for conversion to a voltage signal. A compensation circuit uses both a delay signal from a current-controlled delay circuit receiving the first frequency signal and the first frequency signal to generate a current signal corresponding to the frequency of the latter signal. The voltage signal generated by the low-pass filter is converted into a current signal. This current signal is combined with the current signal from the compensation circuit to control the oscillation frequency of a ring oscillator comprising a current-controlled delay circuit the same in structure as the above current-controlled delay circuit. On the basis of the oscillation signal from the ring oscillator, the second frequency signal and clock signals needed in the semiconductor integrated circuit are generated.
Inventors
- 👤 Kozaburo Kurita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:09
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/0805; H03K; H03K3/00; H03K3/02; H03K3/023; H03K3/0231; H03K3/027; H03K3/03; H03K3/0315; H03K3/0322; H03K5/00; H03K5/13; H03K5/133; H03L7/07; H03L7/081; H03L7/0812; H03L7/0816; H03L7/099; H03L7/0995
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
204 words
A clock pulse generator formed in a semiconductor integrated circuit on a semiconductor substrate, said clock pulse generator comprising: a compensating circuit including: a phase comparator for detecting a phase difference between a timing signal fed from an external terminal of said semiconductor integrated circuit and a clock signal generated within said semiconductor integrated circuit, and for outputting an output signal derived from said phase difference; a low-pass filter for smoothing the output signal of said phase comparator for conversion into a voltage signal; and a first current-controlled delay circuit for generating a delay signal of said timing signal; wherein said compensating circuit uses said timing signal and said delay signal to generate a first current signal corresponding to the frequency of said timing signal; said clock pulse generator further comprising: a voltage-current conversion circuit for converting the voltage signal generated by said low-pass filter into a second current signal, and for generating a third current signal on the basis of said first and said second current signal; and a ring oscillator which, controlled by said third current signal, generates said clock signal by use of a second current-controlled delay circuit having the same circuit constitution as that of said first current-controlled delay circuit.
Claim 2
Dependent Claim
204 words
A clock pulse generator formed in a semiconductor integrated circuit on a semiconductor substrate, said clock pulse generator comprising: a compensating circuit including: a phase comparator for detecting a phase difference between a timing signal fed from an external terminal of said semiconductor integrated circuit and a clock signal generated within said semiconductor integrated circuit, and for outputting an output signal derived from said phase difference; a low-pass filter for smoothing the output signal of said phase comparator for conversion into a voltage signal; and a first current-controlled delay circuit for generating a delay signal of said timing signal; wherein said compensating circuit uses said timing signal and said delay signal to generate a first current signal corresponding to the frequency of said timing signal; said clock pulse generator further comprising: a voltage-current conversion circuit for converting the voltage signal generated by said low-pass filter into a second current signal, and for generating a third current signal on the basis of said first and said second current signal; and a ring oscillator which, controlled by said third current signal, generates said clock signal by use of a second current-controlled delay circuit having the same circuit constitution as that of said first current-controlled delay circuit.
Claim 3
Dependent Claim
86 words
A clock pulse generator according to claim 1, wherein said first and said second current-controlled delay circuit are each composed of a plurality of delay gate circuits, each of said delay gate circuits being constituted by a first p-channel MOSFET and a first n-channel MOSFET for allowing said third current signal to flow therethrough, and by a CMOS inverter circuit which is connected serially between said first p-channel MOSFET and said first n-channel MOSFET and which includes a second p-channel MOSFET and a second n-channel MOSFET.
Claim 4
Dependent Claim
120 words
A clock pulse generator according to claim 1, wherein said first and said second current-controlled delay circuit are each composed of a plurality of delay gate circuits, each of said delay gate circuits including a differential gate circuit constituted by a a first-conductivity type first MOSFET for allowing said third current signal to flow therethrough, by a first-conductivity type second MOSFET and a first-conductivity type third MOSFET having source terminals connected commonly to the drain terminal of said first-conductivity type first MOSFET, and by a second-conductivity type first MOSFET and a second-conductivity type second MOSFET which are connected to the drain terminals of said first-conductivity type second MOSFET and said first-conductivity type third MOSFET and which function as load elements.
Claim 5
Dependent Claim
54 words
A clock pulse generator according to claim 2, further comprising a frequency divider for receiving said clock signal from said ring oscillator and for dividing said clock signal by a predetermined division ratio; wherein the divided clock signal is supplied to predetermined internal circuits of said semiconductor integrated circuit and to said phase comparator.
Claim 6
Dependent Claim
219 words
A clock pulse generator formed in a semiconductor integrated circuit on a semiconductor substrate, said clock pulse generator comprising: a compensation circuit including: a phase comparator for receiving a timing signal fed from an external terminal of said semiconductor integrated circuit and a first delay signal generated by delaying said timing signal, for detecting a phase difference between said timing signal and said first delay signal, and for outputting an output signal derived from said phase difference; a low-pass filter for smoothing the output signal of said phase comparator for conversion into a voltage signal; and a first current-controlled delay circuit for generating a second delay signal of said timing signal; wherein said compensating circuit uses said timing signal and said second delay signal to generate a first current signal corresponding to the frequency of said timing signal; said clock pulse generator further comprising: a voltage-current conversion circuit for converting the voltage signal generated by said low-pass filter into a second current signal, and for generating a third current signal on the basis of said first and said second current signal; and a current gate circuit which, controlled by said third current signal, generates said first delay signal by use of a second current-controlled delay circuit having the same circuit constitution as that of said first current-controlled delay circuit.
Claim 7
Dependent Claim
219 words
A clock pulse generator formed in a semiconductor integrated circuit on a semiconductor substrate, said clock pulse generator comprising: a compensation circuit including: a phase comparator for receiving a timing signal fed from an external terminal of said semiconductor integrated circuit and a first delay signal generated by delaying said timing signal, for detecting a phase difference between said timing signal and said first delay signal, and for outputting an output signal derived from said phase difference; a low-pass filter for smoothing the output signal of said phase comparator for conversion into a voltage signal; and a first current-controlled delay circuit for generating a second delay signal of said timing signal; wherein said compensating circuit uses said timing signal and said second delay signal to generate a first current signal corresponding to the frequency of said timing signal; said clock pulse generator further comprising: a voltage-current conversion circuit for converting the voltage signal generated by said low-pass filter into a second current signal, and for generating a third current signal on the basis of said first and said second current signal; and a current gate circuit which, controlled by said third current signal, generates said first delay signal by use of a second current-controlled delay circuit having the same circuit constitution as that of said first current-controlled delay circuit.
Claim 8
Dependent Claim
31 words
A clock pulse generator according to claim 5, wherein said first delay signal is synchronized with said timing signal and is fed to predetermined internal circuits of said semiconductor integrated circuit.
References Cited (Backward Citations)
JPH02230821A
Cited
US5428309A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-06-09 | 2000-12-09 | 2001-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-09 | 2004-12-09 | 2005-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-09 | 2008-12-09 | 2009-06-10 | $7700.00 | Window Closed / Lapsed |