Patent US6580659B1 successfully refreshed from Google Patents.
US6580659B1
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Burst read addressing in a non-volatile memory device
Assignee: Round Rock Research LLC
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Filing: 2000-08-25
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Granted: 2003-06-17
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Expires: 2020-08-25
Abstract
Abstract A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arranged in a plurality of rows and columns. During a read operation, a row of the memory array can be accessed and data read from a group of columns during a burst operation. The burst columns are generated using an internal counter and an externally provided start address. The memory generates the burst column addresses by modifying the least significant column address signals only. For a burst length of two, only the least significant address bit is modified. For a burst length of four, only the two least significant address bits are modified. Finally, only the three least significant address bit s are modified for a burst length of two. In one embodiment, the burst addresses rotate through the defined column group in a cyclical manner.
Inventors
- 👤 Frankie F. Roohparvar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:08
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1027; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C7/1072; G11C16/32
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
75 words
A synchronous non-volatile memory comprising: an array of non-volatile memory cells arranged in addressable rows and columns; a plurality of column address signal inputs; column address counter circuitry coupled to access the array in response to the plurality of column address signal inputs, the column address counter circuitry identifies any 2 N column addresses of the array by modifying only N least significant column address signal inputs of the plurality of column address signal inputs.
Claim 2
Dependent Claim
75 words
A synchronous non-volatile memory comprising: an array of non-volatile memory cells arranged in addressable rows and columns; a plurality of column address signal inputs; column address counter circuitry coupled to access the array in response to the plurality of column address signal inputs, the column address counter circuitry identifies any 2 N column addresses of the array by modifying only N least significant column address signal inputs of the plurality of column address signal inputs.
Claim 3
Dependent Claim
27 words
The synchronous non-volatile memory of claim 1 further comprising a programmable mode register to store a burst length code indicating a burst length of 2 N .
Claim 4
Dependent Claim
14 words
The synchronous non-volatile memory of claim 2 wherein the programmable mode register is non-volatile.
Claim 5
Dependent Claim
18 words
The synchronous non-volatile memory of claim 1 wherein the plurality of column address signal inputs comprises eight inputs.
Claim 6
Dependent Claim
33 words
The synchronous non-volatile memory of claim 4 wherein 2 N is 2, 4 or 8 and the N least significant column address signal inputs are 1, 2 or 3 column address inputs, respectively.
Claim 7
Dependent Claim
37 words
The synchronous non-volatile memory of claim 1 wherein the column address counter circuitry modifies the N least significant column address signal inputs of the plurality of column address signal inputs in either a linear or interleaved manner.
Claim 8
Dependent Claim
92 words
A synchronous non-volatile memory comprising: an array of non-volatile memory cells arranged in addressable rows and columns; a mode register having programmable storage locations; a plurality of column address signal inputs; and column address counter circuitry coupled to access the array in response to the plurality of column address signal inputs and the programmable storage locations of the mode register, the column address counter circuitry counts 2 N consecutive column addresses of the array by modifying only N least significant column address signal inputs of the plurality of column address signal inputs.
Claim 9
Dependent Claim
92 words
A synchronous non-volatile memory comprising: an array of non-volatile memory cells arranged in addressable rows and columns; a mode register having programmable storage locations; a plurality of column address signal inputs; and column address counter circuitry coupled to access the array in response to the plurality of column address signal inputs and the programmable storage locations of the mode register, the column address counter circuitry counts 2 N consecutive column addresses of the array by modifying only N least significant column address signal inputs of the plurality of column address signal inputs.
Claim 10
Dependent Claim
18 words
The synchronous non-volatile memory of claim 7 wherein the mode register wherein the programmable storage locations are non-volatile.
Claim 11
Dependent Claim
33 words
The synchronous non-volatile memory of claim 7 wherein 2 N is 2, 4 or 8 and the N least significant column address signal inputs are 1, 2 or 3 column address inputs, respectively.
Claim 12
Dependent Claim
37 words
The synchronous non-volatile memory of claim 7 wherein the column address counter circuitry modifies the N least significant column address signal inputs of the plurality of column address signal inputs in either a linear or interleaved manner.
Claim 13
Dependent Claim
113 words
A memory system comprising: a memory controller; and a synchronous non-volatile memory coupled to the memory controller and comprising, an array of non-volatile memory cells arranged in addressable rows and columns, a mode register having programmable storage locations, a plurality of column address signal inputs to receive address signals from the memory controller, and column address counter circuitry coupled to access the array in response to the plurality of column address signal inputs and the programmable storage locations of the mode register, the column address counter circuitry counts 2 N column addresses of the array by modifying only N least significant column address signal inputs of the plurality of column address signal inputs.
Claim 14
Dependent Claim
113 words
A memory system comprising: a memory controller; and a synchronous non-volatile memory coupled to the memory controller and comprising, an array of non-volatile memory cells arranged in addressable rows and columns, a mode register having programmable storage locations, a plurality of column address signal inputs to receive address signals from the memory controller, and column address counter circuitry coupled to access the array in response to the plurality of column address signal inputs and the programmable storage locations of the mode register, the column address counter circuitry counts 2 N column addresses of the array by modifying only N least significant column address signal inputs of the plurality of column address signal inputs.
Claim 15
Dependent Claim
44 words
The memory system of claim 11 wherein the plurality of column address signal inputs comprises eight inputs, and wherein 2 N is 2, 4 or 8 and the N least significant column address signal inputs are 1, 2 or 3 column address inputs, respectively.
Claim 16
Dependent Claim
36 words
The memory system of claim 11 wherein the column address counter circuitry modifies the N least significant column address signal inputs of the plurality of column address signal inputs in either a linear or interleaved manner.
Claim 17
Independent Claim
69 words
A method of burst reading a non-volatile synchronous memory device comprising: receiving an externally provided initial column address; and generating a series of column addresses using an internal address counter, the series of column addresses starts at the externally provided initial column address, wherein the series of column addresses comprise 2 N column addresses and the series is generated by modifying only N least significant column address signal inputs.
Claim 18
Independent Claim
69 words
A method of burst reading a non-volatile synchronous memory device comprising: receiving an externally provided initial column address; and generating a series of column addresses using an internal address counter, the series of column addresses starts at the externally provided initial column address, wherein the series of column addresses comprise 2 N column addresses and the series is generated by modifying only N least significant column address signal inputs.
Claim 19
Dependent Claim
24 words
The method of claim 14 wherein 2 N is 4 and the N least significant column address signal inputs are 2 column address inputs.
Claim 20
Dependent Claim
24 words
The method of claim 14 wherein 2 N is 8 and the N least significant column address signal inputs are 3 column address inputs.
Claim 21
Dependent Claim
23 words
The method of claim 14 wherein the N least significant column address signal inputs are modified in either a linear or interleaved manner.
Claim 22
Independent Claim
101 words
A method of reading a non-volatile synchronous memory device comprising: initiating a burst read operation by providing control signals from an processor device coupled to the non-volatile synchronous memory device; coupling an initial column address from the processor to the non-volatile synchronous memory device; and generating a series of column addresses using an internal address counter of the non-volatile synchronous memory device, the series of column addresses starts at the externally provided initial column address, wherein the series of column addresses comprise 2 N column addresses and the series is generated by modifying only N least significant column address signal inputs.
Claim 23
Independent Claim
101 words
A method of reading a non-volatile synchronous memory device comprising: initiating a burst read operation by providing control signals from an processor device coupled to the non-volatile synchronous memory device; coupling an initial column address from the processor to the non-volatile synchronous memory device; and generating a series of column addresses using an internal address counter of the non-volatile synchronous memory device, the series of column addresses starts at the externally provided initial column address, wherein the series of column addresses comprise 2 N column addresses and the series is generated by modifying only N least significant column address signal inputs.
Claim 24
Dependent Claim
31 words
The method of claim 18 wherein 2 N is 2, 4 or 8 and the N least significant column address signal inputs are 1, 2 or 3 column address inputs, respectively.
Claim 25
Dependent Claim
23 words
The method of claim 18 wherein the N least significant column address signal inputs are modified in either a linear or interleaved manner.
References Cited (Backward Citations)
US5041886A
Cited
US5537354A
Cited
US6026465A
Cited
US5668773A
Cited
US5751039A
Cited
US6137133A
Cited
US5600605A
Cited
US5666321A
Cited
US5986943A
Cited
US5966724A
Cited
US5749086A
Cited
US6122718A
Cited
US5787457A
Cited
US5974514A
Cited
US5936903A
Cited
US5995438A
Cited
US6038196A
Cited
US6172935B1
Cited
US6141247A
Cited
US6229759B1
Cited
US6028812A
Cited
US6091665A
Cited
US6192002B1
Cited
US6108265A
Cited
US6125078A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-06-16 | 2006-12-16 | 2007-06-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-06-16 | 2010-12-16 | 2011-06-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-06-16 | 2014-12-16 | 2015-06-17 | $7700.00 | Window Closed / Lapsed |