Semiconductor memory device having a synchronous DRAM

Claim 2

A semiconductor memory device comprising: a) a control/address input device controlled by address and control signals; b) a row and column address counter operated by an output signal of said control/address input device; c) a column address decoder to which output signals of said control/address input device and said row and column address counter are input; d) a row address decoder to which output signals of said control/address input device and said row and column address counter are input; and e) a memory cell array operated by output signals of said row address decoder and column address decoder; wherein said row and column address counter includes: 1) a first unit row and column counter for outputting: 1a) a first column count signal and 1b) a first row count signal; according to: 1c) a column control signal and 1d) a row control signal; 2) a second unit row and column counter for outputting: 2a) a second column count signal and 2b) a second row count signal; according to: 2c) said column control signal, 2d) said row control signal, 2e) said first column count signal and 2f) said first row count signal; and 3) at least one gate for logically operating on: 3a) said first column count signal and 3b) said second column count signal: and for providing an output to a third unit row and column counter.

Claim 3

A semiconductor memory device comprising: a) a control/address input device controlled by address and control signals; b) a row and column address counter operated by an output signal of said control/address input device; c) a column address decoder to which output signals of said control/address input device and said row and column address counter are input; d) a row address decoder to which output signals of said control/address input device and said row and column address counter are input; and e) a memory cell array operated by output signals of said row address decoder and column address decoder; wherein said row and column address counter includes: 1) a first unit row and column counter for outputting: 1a) a first column count signal and 1b) a first row count signal; according to: 1c) a column control signal and 1d) a row control signal; 2) a second unit row and column counter for outputting: 2a) a second column count signal and 2b) a second row count signal; according to: 2c) said column control signal, 2d) said row control signal, 2e) said first column count signal and 2f) said first row count signal; 3) a first AND gate for logically operating on: 3a) said first column count signal and 3b) said second column count signal; and for providing an output to: 3c) a third unit row and column counter, and 3d) a terminal of a third AND gate; 4) a second AND gate for logically operating on: 4a) said first row count signal and 4b) said second row count signal; and for providing an output to: 4c) said third unit row and column counter, and 4d) a terminal of a fourth AND gate; 5) said third unit row and column counter for outputting: 5a) a third column count signal and 5b) a third row count signal; according to: 5c) said column control signal, 5d) said row control signal, and 5e) the outputs of said first and second AND gates; 6) said third AND gate for logically operating on: 6a) the output of said first AND gate and 6b) said third column count signal; and for providing an output to: 6c) a fourth unit row and column counter, and 6d) a terminal of a fifth AND gate; 7) said fourth AND gate for logically operating on: 7a) the output of said second AND gate and 7b) said third row count signal; and for providing an output to: 7c) said fourth unit row and column counter, and 7d) a terminal of a sixth AND gate; and 8) a nth row and column counter for outputting: 8a) a nth column count signal and 8b) a nth row count signal; according to: 8c) said column control signal, 8d) said row control signal, 8e) an output signal of a (2n-3)th AND gate and 8f) an output signal of a (2n-2)th AND gate, wherein n is an integer 2, 3 . . . .

Claim 4

A semiconductor memory device comprising: a) a control/address input device controlled by address and control signals; b) a row and column address counter operated by an output signal of said control/address input device; c) a column address decoder to which output signals of said control/address input device and said row and column address counter are input; d) a row address decoder to which output signals of said control/address input device and said row and column address counter are input; and e) a memory cell array operated by output signals of said row address decoder and column address decoder; wherein said row and column address counter includes: 1) a first unit row and column counter for outputting: 1a) a first column count signal and 1b) a first row count signal; according to: 1c) a column control signal and 1d) a row control signal; 2) a second unit row and column counter for outputting: 2a) a second column count signal and 2b) a second row count signal; according to: 2c) said column control signal, 2d) said row control signal, 2e) said first column count signal and 2f) said first row count signal; 3) a first AND gate for logically operating on: 3a) said first column count signal and 3b) said second column count signal; and for providing an output to: 3c) a third unit row and column counter, and 3d) a terminal of a third AND gate; 4) a second AND gate for logically operating on: 4a) said first row count signal and 4b) said second row count signal; and for providing an output to: 4c) said third unit row and column counter, and 4d) a terminal of a fourth AND gate; 5) said third unit row and column counter for outputting: 5a) a third column count signal and 5b) a third row count signal; according to: 5c) said column control signal, 5d) said row control signal, and 5e) the outputs of said first and second AND gates; 6) said third AND gate for logically operating on: 6a) the output of said first AND gate and 6b) said third column count signal; and for providing an output to: 6c) a fourth unit row and column counter, and 6d) a terminal of a fifth AND gate; 7) said fourth AND gate for logically operating on: 7a) the output of said second AND gate and 7b) said third row count signal; and for providing an output to: 7c) said fourth unit row and column counter, and 7d) a terminal of a sixth AND gate; and 8) a nth row and column counter for outputting: 8a) a nth column count signal and 8b) a nth row count signal; according to: 8c) said column control signal, 8d) said row control signal, 8e) an output signal of a (2n-3)th AND gate and 8f) an output signal of a (2n-2)th AND gate, wherein n is an integer 2, 3 . . . .

Claim 5

A semiconductor memory device comprising: a) a control/address input device controlled by address and control signals; b) a row and column address counter operated by an output signal of said control/address input device; c) a column address decoder to which output signals of said control/address input device and said row and column address counter are input; d) a row address decoder to which output signals of said control/address input device and said row and column address counter are input; and e) a memory cell array operated by output signals of said row address decoder and column address decoder; wherein said row and column address counter includes at least one unit row and column counter that includes: 1) a first transmission gate for outputting a column increment signal to a first terminal of a NOR gate according to a column count signal; 2) a second transmission gate for outputting a row increment signal to a second terminal of said NOR gate according to a row count signal; and 3) said NOR gate for logically operating on said column increment signal and said row increment signal and for outputting a signal adapted to control tri-state inverters.

Claim 6

A semiconductor memory device comprising: a) a control/address input device controlled by address and control signals; b) a row and column address counter operated by an output signal of said control/address input device; c) a column address decoder to which output signals of said control/address input device and said row and column address counter are input; d) a row address decoder to which output signals of said control/address input device and said row and column address counter are input; and e) a memory cell array operated by output signals of said row address decoder and column address decoder; wherein said row and column address counter includes at least one unit row and column counter that includes: 1) a first transmission gate for outputting a column increment signal to a first terminal of a NOR gate according to a column count signal; 2) a second transmission gate for outputting a row increment signal to a second terminal of said NOR gate according to a row count signal; and 3) said NOR gate for logically operating on said column increment signal and said row increment signal and for outputting a signal adapted to control tri-state inverters.

Claim 7

A semiconductor memory device comprising: a) a control/address input device controlled by address and control signals; b) a row and column address counter operated by an output signal of said control/address input device; c) a column address decoder to which output signals of said control/address input device and said row and column address counter are input; d) a row address decoder to which output signals of said control/address input device and said row and column address counter are input; and e) a memory cell array operated by output signals of said row address decoder and column address decoder; wherein said row and column address counter includes a unit row and column address counter that includes: 1) a first transmission gate for outputting a start address signal for burst write and read operation to a first tri-state inverter and an output terminal of a second transmission gate, wherein said first transmission gate is controlled by a signal to initialize unit row and column counters; 2) said second transmission gate for outputting an output signal of a third transmission gate, wherein said second transmission gate is controlled by the signal to initialize said unit row and column counters by means of a refresh address; and 3) said first tri-state inverter, and second and third tri-state inverters, and a fourth transmission gate for outputting a column count signal in response to an output signal of said second transmission gate.

Claim 8

A semiconductor memory device comprising: a) a control/address input device controlled by address and control signals; b) a row and column address counter operated by an output signal of said control/address input device; c) a column address decoder to which output signals of said control/address input device and said row and column address counter are input; d) a row address decoder to which output signals of said control/address input device and said row and column address counter are input; and e) a memory cell array operated by output signals of said row address decoder and column address decoder; wherein said row and column address counter includes a unit row and column address counter that includes: 1) a first transmission gate for outputting a start address signal for burst write and read operation to a first tri-state inverter and an output terminal of a second transmission gate, wherein said first transmission gate is controlled by a signal to initialize unit row and column counters; 2) said second transmission gate for outputting an output signal of a third transmission gate, wherein said second transmission gate is controlled by the signal to initialize said unit row and column counters by means of a refresh address; and 3) said first tri-state inverter, and second and third tri-state inverters, and a fourth transmission gate for outputting a column count signal in response to an output signal of said second transmission gate.

Claim 9

A semiconductor memory device comprising: a) a control/address input device controlled by address and control signals; b) a row and column address counter operated by an output signal of said control/address input device; c) a column address decoder to which output signals of said control/address input device and said row and column address counter are input; d) a row address decoder to which output signals of said control/address input device and said row and column address counter are input; and e) a memory cell array operated by output signals of said row address decoder and column address decoder; wherein said row and column address counter includes at least one unit row and column counter that includes: 1) a first transmission gate for outputting a column increment signal to a NOR gate, wherein said first transmission gate is controlled by a column count signal; 2) a second transmission gate for outputting a row increment signal to an output terminal of said NOR gate in response to a row count signal; 3) said NOR gate for logically combining said column increment signal and said row increment signal, thereby outputting a signal adapted to control tri-state inverters; 4) a third transmission gate for outputting a start address for a burst write and read operation to a first tri-state inverter and a fourth transmission gate, wherein said third transmission gate is controlled by a signal to initialize unit row and column counters; 5) said fourth transmission gate, controlled by the signal to initialize said unit row and column counters by a refresh address, wherein said fourth transmission gate outputs an output signal of a fifth transmission gate; 6) said fifth transmission gate for outputting an output signal of said first tri-state inverter to said fourth transmission gate, wherein said fifth transmission gate is controlled by a refresh enable signal; and 7) said first tri-state inverter, and second and third tri-state inverters, and a sixth transmission gate for outputting a column count signal in response to an output signal of said fourth transmission gate.

Claim 10

A semiconductor memory device comprising: a) a control/address input device controlled by address and control signals; b) a row and column address counter operated by an output signal of said control/address input device; c) a column address decoder to which output signals of said control/address input device and said row and column address counter are input; d) a row address decoder to which output signals of said control/address input device and said row and column address counter are input; and e) a memory cell array operated by output signals of said row address decoder and column address decoder; wherein said row and column address counter includes at least one unit row and column counter that includes: 1) a first transmission gate for outputting a column increment signal to a NOR gate, wherein said first transmission gate is controlled by a column count signal; 2) a second transmission gate for outputting a row increment signal to an output terminal of said NOR gate in response to a row count signal; 3) said NOR gate for logically combining said column increment signal and said row increment signal, thereby outputting a signal adapted to control tri-state inverters; 4) a third transmission gate for outputting a start address for a burst write and read operation to a first tri-state inverter and a fourth transmission gate, wherein said third transmission gate is controlled by a signal to initialize unit row and column counters; 5) said fourth transmission gate, controlled by the signal to initialize said unit row and column counters by a refresh address, wherein said fourth transmission gate outputs an output signal of a fifth transmission gate; 6) said fifth transmission gate for outputting an output signal of said first tri-state inverter to said fourth transmission gate, wherein said fifth transmission gate is controlled by a refresh enable signal; and 7) said first tri-state inverter, and second and third tri-state inverters, and a sixth transmission gate for outputting a column count signal in response to an output signal of said fourth transmission gate.