US6229759B1
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Semiconductor memory burst length count determination method
Assignee: Micron Technology Inc
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Filing: 2000-04-18
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Granted: 2001-05-08
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Expires: 2020-04-18
Abstract
Abstract The present invention is directed to a circuit for detecting the end of a burst count in a semiconductor memory device. The circuit is responsive to a plurality of burst counter output bits and a plurality of burst length selection bits. The circuit is comprised of an array of individual semiconductor devices responsive to the burst counter output bits and the burst length selection bits for producing a transition in an output signal when the burst counter output bits are at a logical combination determined by the burst length selection bits. A method for detecting the end of a burst count in a semiconductor memory device is also disclosed.
Inventors
- 👤 Donald Morgan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 19:26
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
100 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: receiving a plurality of output bits from a burst counter and a plurality of burst length selection bits; driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; and driving the dynamic node to a second voltage representative of a second logic state by discharging the dynamic node through certain of the semiconductor devices when the burst counter output bits reach a predetermined count, the predetermined count determined by the burst length selection bits.
Claim 2
Independent Claim
100 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: receiving a plurality of output bits from a burst counter and a plurality of burst length selection bits; driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; and driving the dynamic node to a second voltage representative of a second logic state by discharging the dynamic node through certain of the semiconductor devices when the burst counter output bits reach a predetermined count, the predetermined count determined by the burst length selection bits.
Claim 3
Dependent Claim
66 words
The method of claim 1 , wherein: driving a dynamic node to a first voltage representative of a first logic state includes driving the dynamic node to a first voltage representative of a logic high state; and driving the dynamic node to a second voltage representative of a second logic state includes driving the dynamic node to a second voltage representative of a logic low state.
Claim 4
Dependent Claim
34 words
The method of claim 1 , wherein driving the dynamic node to a first voltage representative of a first logic state includes charging the dynamic node to the first voltage via a pull-up transistor.
Claim 5
Independent Claim
92 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: receiving a plurality of burst counter bits; receiving a plurality of burst length selection bits indicative of a burst length count; driving a dynamic node of an array of transistors to a first voltage representative of a first logic state; and driving the dynamic node to a second voltage representative of a second logic state by discharging the dynamic node through certain of the transistors when the burst counter output bits reach the burst length count.
Claim 6
Independent Claim
92 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: receiving a plurality of burst counter bits; receiving a plurality of burst length selection bits indicative of a burst length count; driving a dynamic node of an array of transistors to a first voltage representative of a first logic state; and driving the dynamic node to a second voltage representative of a second logic state by discharging the dynamic node through certain of the transistors when the burst counter output bits reach the burst length count.
Claim 7
Dependent Claim
45 words
The method of claim 4 , wherein discharging the dynamic node through certain of the transistors includes providing a conduction path between the dynamic node and a static node through certain of the transistors when the burst counter output bits reach the burst length count.
Claim 8
Dependent Claim
100 words
The method of claim 5 , wherein providing a conduction path between the dynamic node and a static node through certain of the transistors includes: gating a first plurality of the transistors with a separate burst counter bit; gating a second plurality of the transistors with a separate burst length selection bit; and configuring the array of transistors such that a conduction path is provided between the dynamic node and the static node through one of the first plurality of transistors and one of the second plurality of transistors when the burst counter output bits reach the burst length count.
Claim 9
Dependent Claim
62 words
The method of claim 6 , wherein configuring the array of transistors includes configuring the array of transistors such that a conduction path is provided between the dynamic node and the static node through one of the first plurality of transistors and at least one of the second plurality of transistors when the burst counter output bits reach the burst length count.
Claim 10
Independent Claim
90 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; and driving the dynamic node to a second voltage representative of a second logic state by discharging the dynamic node through certain of the semiconductor devices when output bits from a burst counter of the semiconductor memory device reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits.
Claim 11
Independent Claim
90 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; and driving the dynamic node to a second voltage representative of a second logic state by discharging the dynamic node through certain of the semiconductor devices when output bits from a burst counter of the semiconductor memory device reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits.
Claim 12
Dependent Claim
46 words
The method of claim 8 , wherein discharging the dynamic node through certain of the transistors includes providing a conduction path between the dynamic node and a static node through certain of the semiconductor devices when the burst counter output bits reach the burst length count.
Claim 13
Dependent Claim
122 words
The method of claim 9 , wherein providing a conduction path between the dynamic node and a static node through certain of the semiconductor devices includes: biasing a first plurality of the semiconductor devices between a conductive state and a non-conductive state with a separate burst counter bit; biasing a second plurality of the semiconductor devices between a conductive state and a non-conductive state with a separate burst length selection bit; and configuring the array of semiconductor devices such that a conduction path is provided between the dynamic node and the static node through one of the first plurality of semiconductor devices and one of the second plurality of semiconductor devices when the burst counter output bits reach the burst length count.
Claim 14
Independent Claim
98 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; and driving the dynamic node to a second voltage representative of a second logic state when output bits from a burst counter of the semiconductor memory device reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits, wherein a count representative of the output bits is incremented by one at each pulse of a system clock.
Claim 15
Independent Claim
98 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; and driving the dynamic node to a second voltage representative of a second logic state when output bits from a burst counter of the semiconductor memory device reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits, wherein a count representative of the output bits is incremented by one at each pulse of a system clock.
Claim 16
Independent Claim
83 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: resetting a burst counter of the semiconductor memory device; driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; and driving the dynamic node to a second voltage representative of a second logic state when output bits from the burst counter reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits.
Claim 17
Independent Claim
83 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: resetting a burst counter of the semiconductor memory device; driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; and driving the dynamic node to a second voltage representative of a second logic state when output bits from the burst counter reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits.
Claim 18
Dependent Claim
28 words
The method of claim 12 , wherein resetting the burst counter includes resetting the burst counter when one of a read opcode and a write opcode is detected.
Claim 19
Dependent Claim
37 words
The method of claim 13 , wherein resetting the burst counter includes resetting the burst counter when one of a read opcode and a write opcode is detected by a decoder circuit of the semiconductor memory device.
Claim 20
Independent Claim
104 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: resetting a burst counter of the semiconductor memory device; driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; incrementing a count represented by output bits of the burst counter by one at each pulse of a system clock; and driving the dynamic node to a second voltage representative of a second logic state when the output bits of the burst counter reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits.
Claim 21
Independent Claim
104 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: resetting a burst counter of the semiconductor memory device; driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; incrementing a count represented by output bits of the burst counter by one at each pulse of a system clock; and driving the dynamic node to a second voltage representative of a second logic state when the output bits of the burst counter reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits.
Claim 22
Independent Claim
95 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: resetting a burst counter of the semiconductor memory device when one of a read opcode and a write opcode is validated; driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; and driving the dynamic node to a second voltage representative of a second logic state when output bits from the burst counter reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits.
Claim 23
Independent Claim
95 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: resetting a burst counter of the semiconductor memory device when one of a read opcode and a write opcode is validated; driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; and driving the dynamic node to a second voltage representative of a second logic state when output bits from the burst counter reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits.
Claim 24
Dependent Claim
21 words
The method of claim 16 , further comprising retaining a voltage of the dynamic node when the opcode is not validated.
Claim 25
Independent Claim
104 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: incrementing by one a count represented by output bits of a burst counter of the semiconductor memory device at each pulse of a system clock; driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; and driving the dynamic node to a second voltage representative of a second logic state when output bits from a burst counter of the semiconductor memory device reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits.
Claim 26
Independent Claim
104 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: incrementing by one a count represented by output bits of a burst counter of the semiconductor memory device at each pulse of a system clock; driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; and driving the dynamic node to a second voltage representative of a second logic state when output bits from a burst counter of the semiconductor memory device reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits.
Claim 27
Independent Claim
94 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: incrementing by one a count represented by output bits of a burst counter of the semiconductor memory at each pulse of a system clock; driving a dynamic node of an array of transistors to a first voltage representative of a first logic state; and discharging the dynamic node through certain of the transistors when the burst counter output bits reach the a burst length count, the burst length count determined by a plurality of burst length selection bits.
Claim 28
Independent Claim
94 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: incrementing by one a count represented by output bits of a burst counter of the semiconductor memory at each pulse of a system clock; driving a dynamic node of an array of transistors to a first voltage representative of a first logic state; and discharging the dynamic node through certain of the transistors when the burst counter output bits reach the a burst length count, the burst length count determined by a plurality of burst length selection bits.
Claim 29
Dependent Claim
71 words
The method of claim 19 , wherein discharging the dynamic node includes: gating a first plurality of the transistors with a separate output bit from the burst counter; gating a second plurality of the transistors with a separate burst length selection bit; and configuring the array of transistors such that a conduction path is provided between the dynamic node and a static node when the output bits reach the burst count.
Claim 30
Independent Claim
153 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; driving the dynamic node to a second voltage representative of a second logic state when output bits from a burst counter of the semiconductor memory device reach a first burst length count, the first burst length count determined by a plurality of burst length selection bits; resetting the output bits from the burst counter; driving a dynamic node of an array of semiconductor devices to the first voltage representative of the first logic state; and driving the dynamic node to a second voltage representative of the second logic state when the output bits from the burst counter reach a second burst length count, the second burst length count determined by a plurality of burst length selection bits.
Claim 31
Independent Claim
153 words
A method for detecting an end of a burst count in a semiconductor memory device, comprising: driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state; driving the dynamic node to a second voltage representative of a second logic state when output bits from a burst counter of the semiconductor memory device reach a first burst length count, the first burst length count determined by a plurality of burst length selection bits; resetting the output bits from the burst counter; driving a dynamic node of an array of semiconductor devices to the first voltage representative of the first logic state; and driving the dynamic node to a second voltage representative of the second logic state when the output bits from the burst counter reach a second burst length count, the second burst length count determined by a plurality of burst length selection bits.
Claim 32
Dependent Claim
36 words
The method of claim 21 , wherein resetting the output bits from the burst counter includes resetting the output bits from the burst counter when one of a read opcode and a write opcode is detected.
Claim 33
Dependent Claim
38 words
The method of claim 21 , wherein resetting the output bits from the burst counter includes resetting the output bits from the burst counter when one of a read opcode and a write opcode is detected and validated.
Claim 34
Dependent Claim
73 words
The method of claim 21 , wherein driving the dynamic node to a second voltage representative of the second logic state when the output bits from the burst counter reach a second burst length count includes driving the dynamic node to a second voltage representative of the second logic state when the output bits from the burst counter reach a second burst length count which is unequal to the first burst length count.
Claim 35
Independent Claim
105 words
A method of operating a semiconductor memory device, comprising: driving a dynamic node of an array of semiconductor devices of the semiconductor device to a first voltage representative of a first logic state; driving the dynamic node to a second voltage representative of a second logic state when output bits from a burst counter of the semiconductor memory device reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits; generating an address when the dynamic node is driven to the second voltage; and supplying the address to a column decoder of a memory array of the semiconductor memory device.
Claim 36
Independent Claim
105 words
A method of operating a semiconductor memory device, comprising: driving a dynamic node of an array of semiconductor devices of the semiconductor device to a first voltage representative of a first logic state; driving the dynamic node to a second voltage representative of a second logic state when output bits from a burst counter of the semiconductor memory device reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits; generating an address when the dynamic node is driven to the second voltage; and supplying the address to a column decoder of a memory array of the semiconductor memory device.
Claim 37
Dependent Claim
54 words
The method of claim 25 , wherein generating an address includes activating a column address counter of the semiconductor memory device when the dynamic node is driven to the second voltage, and wherein supplying the address to the column decoder includes supplying the address generated by the column address counter to the column decoder.
Claim 38
Dependent Claim
37 words
The method of claim 26 , wherein activating the column address counter includes outputting a signal indicative of the first logic state to the column address counter when the dynamic node is driven to the second voltage.
Claim 39
Independent Claim
134 words
A method of operating a semiconductor memory device, comprising: driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state when one of a read command and a write command is received by the semiconductor memory device from an external controller; driving the dynamic node to a second voltage representative of a second logic state when output bits from a burst counter of the semiconductor memory device reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits received by the semiconductor memory device from the external controller; generating an address when the dynamic node is driven to the second voltage; and supplying the address to a column decoder of a memory array of the of the semiconductor memory device.
Claim 40
Independent Claim
134 words
A method of operating a semiconductor memory device, comprising: driving a dynamic node of an array of semiconductor devices to a first voltage representative of a first logic state when one of a read command and a write command is received by the semiconductor memory device from an external controller; driving the dynamic node to a second voltage representative of a second logic state when output bits from a burst counter of the semiconductor memory device reach a predetermined count, the predetermined count determined by a plurality of burst length selection bits received by the semiconductor memory device from the external controller; generating an address when the dynamic node is driven to the second voltage; and supplying the address to a column decoder of a memory array of the of the semiconductor memory device.
Claim 41
Dependent Claim
29 words
The method of claim 28 , wherein generating the address includes generating an address based on an initial address supplied to the semiconductor memory device from the external controller.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-07 | 2004-11-06 | 2005-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-07 | 2008-11-06 | 2009-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-07 | 2012-11-06 | 2013-05-08 | $7700.00 | Window Closed / Lapsed |