US5610874A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fast burst-mode synchronous random access memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1994-11-07
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Granted: 1997-03-11
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Expires: 2014-11-07
Abstract
Abstract A synchronous random access memory device having an external address mode of operation and a burst mode of operation, in which a counter control circuit resets a burst mode counter during the external address mode of operation.
Inventors
- 👤 Hee-Chail Park
- 👤 Kook-Hwan Kweon
- 👤 Jeon-Taek Im
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 00:43
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1072
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
60 words
A memory device having an external address mode of operation and a burst mode of operation, comprising: a counter control circuit which generates a counter reset signal during an external address mode of operation; and a counter circuit for generating a counter output during a burst mode of operation, wherein said counter circuit is reset by said counter reset signal.
Claim 2
Dependent Claim
60 words
A memory device having an external address mode of operation and a burst mode of operation, comprising: a counter control circuit which generates a counter reset signal during an external address mode of operation; and a counter circuit for generating a counter output during a burst mode of operation, wherein said counter circuit is reset by said counter reset signal.
Claim 3
Dependent Claim
30 words
A memory device according to claim 1, wherein said counter control circuit generates said counter reset signal when said memory device is placed in said external address mode of operation.
Claim 4
Dependent Claim
15 words
A memory device according to claim 1, wherein said counter output comprises internal address signals.
Claim 5
Dependent Claim
44 words
A memory device according to claim 1, further comprising: an internal address generation circuit responsive to said counter output, wherein during said burst mode of operation said internal address generation circuit generates an internal address based on an external address and said counter output.
Claim 6
Dependent Claim
24 words
A memory device according to claim 1, further comprising: an address buffer for receiving an external address during said external address mode of operation.
Claim 7
Dependent Claim
68 words
A memory device comprising: an external mode of operation for receiving external address signals and a burst mode of operation for generating internal address signals; a counter control circuit which generates a counter reset signal during said external address mode of operation; and a counter circuit for generating a counter output during said burst mode of operation, wherein said counter circuit is reset by said counter reset signal.
Claim 8
Dependent Claim
68 words
A memory device comprising: an external mode of operation for receiving external address signals and a burst mode of operation for generating internal address signals; a counter control circuit which generates a counter reset signal during said external address mode of operation; and a counter circuit for generating a counter output during said burst mode of operation, wherein said counter circuit is reset by said counter reset signal.
Claim 9
Independent Claim
60 words
A method of controlling a burst mode counter in a memory device comprising the steps of: placing said memory device in an external address mode of operation; resetting a burst mode counter during said external address mode of operation; and enabling said burst mode counter during a burst mode of operation, wherein said burst mode counter generates internal address signals.
Claim 10
Independent Claim
60 words
A method of controlling a burst mode counter in a memory device comprising the steps of: placing said memory device in an external address mode of operation; resetting a burst mode counter during said external address mode of operation; and enabling said burst mode counter during a burst mode of operation, wherein said burst mode counter generates internal address signals.
Claim 11
Independent Claim
63 words
A method of operating a memory device comprising the steps of: placing said memory device in an external address mode of operation; resetting a burst mode counter during said external address mode of operation; and generating an internal address during a burst mode of operation, wherein said internal address is based on an external address and an output of said burst mode counter.
Claim 12
Independent Claim
63 words
A method of operating a memory device comprising the steps of: placing said memory device in an external address mode of operation; resetting a burst mode counter during said external address mode of operation; and generating an internal address during a burst mode of operation, wherein said internal address is based on an external address and an output of said burst mode counter.
Claim 13
Dependent Claim
25 words
The method according to claim 7, wherein said burst mode counter is reset when said memory device is placed in said external mode of operation.
Claim 14
Dependent Claim
25 words
The method according to claim 8, wherein said burst mode counter is reset when said memory device is placed in said external mode of operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-10 | 2000-09-09 | 2001-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-10 | 2004-09-09 | 2005-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-10 | 2008-09-09 | 2009-03-11 | $7700.00 | Window Closed / Lapsed |