US6141247A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile data storage unit and method of controlling same
Assignee: Round Rock Research LLC
•
Filing: 1998-12-21
•
Granted: 2000-10-31
•
Expires: 2018-12-21
Abstract
Abstract A non-volatile data storage unit having a data input and a volatile memory device for storing data. The volatile memory device is preferably a latch circuit made up of a pair of cross-coupled inverter circuits which store the data in complementary form. A non-volatile memory device, such as a pair of flash memory cells, is included which also store data in complementary form. Control circuitry is provided for controlling the operation of the data storage unit, including circuitry for transferring data from the data input to the volatile memory device and circuitry for programming the non-volatile memory device with data from the volatile memory device. The storage unit also preferably includes circuitry for transferring data stored in the non-volatile memory device to the volatile memory device, with such transfer typically taking place after an interruption of power to the storage unit.
Inventors
- 👤 Frankie F. Roohparvar
- 👤 Michael S. Briner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:56
CPC Classifications
G; G11; G11C; G11C14/00
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
90 words
An integrated circuit, operable in one of a plurality of operating modes, comprising: an input connection for receiving an input signal, the input signal is used to select the one of the plurality of operating modes; a first latch circuit coupled to the input connection to volatilely store the input signal; a second latch coupled to input connection and the first latch for non-volatilely storing the input signal; and a comparator to compare the input signal on the input connection with data stored in either the first or second latch.
Claim 2
Dependent Claim
90 words
An integrated circuit, operable in one of a plurality of operating modes, comprising: an input connection for receiving an input signal, the input signal is used to select the one of the plurality of operating modes; a first latch circuit coupled to the input connection to volatilely store the input signal; a second latch coupled to input connection and the first latch for non-volatilely storing the input signal; and a comparator to compare the input signal on the input connection with data stored in either the first or second latch.
Claim 3
Dependent Claim
16 words
The integrated circuit of claim 1 wherein the first latch circuit is an inverter logic circuit.
Claim 4
Dependent Claim
17 words
The integrated circuit of claim 1 wherein the second latch circuit is a floating gate memory cell.
Claim 5
Dependent Claim
93 words
An integrated circuit, operable in one of a plurality of operating modes, comprising: first and second input connections for receiving an complementary input signals, the input signals are used to select the one of the plurality of operating modes; a first latch circuit coupled to the input connections to volatilely store the input signals; a second latch coupled to input connections and the first latch for non-volatilely storing the input signals; and a comparator to compare the input signal on the input connection with data stored in either the first or second latch.
Claim 6
Dependent Claim
93 words
An integrated circuit, operable in one of a plurality of operating modes, comprising: first and second input connections for receiving an complementary input signals, the input signals are used to select the one of the plurality of operating modes; a first latch circuit coupled to the input connections to volatilely store the input signals; a second latch coupled to input connections and the first latch for non-volatilely storing the input signals; and a comparator to compare the input signal on the input connection with data stored in either the first or second latch.
Claim 7
Dependent Claim
35 words
The integrated circuit of claim 4 wherein the first latch circuit comprises: a first inverter logic circuit coupled to the first input connection; and a second inverter logic circuit coupled to the second input connection.
Claim 8
Dependent Claim
39 words
The integrated circuit of claim 5 wherein the second latch circuit comprises: a first floating gate memory cell coupled to the first inverter logic circuit; and a second floating gate memory cell coupled to the second inverter logic circuit.
Claim 9
Dependent Claim
26 words
The integrated circuit of claim 4 wherein the second latch circuit comprises a pair of floating gate memory cells coupled to receive the complementary input signals.
Claim 10
Dependent Claim
86 words
An integrated circuit, operable in one of a plurality of operating modes, comprising: an input connection for receiving an input signal, the input signal is used to select the one of the plurality of operating modes; a first isolation circuit coupled to the input connection; a first latch circuit coupled to the first isolation circuit to volatilely store the input signal; a second isolation circuit coupled to the first latch circuit; and a second latch coupled to second isolation circuit to non-volatilely store the input signal.
Claim 11
Dependent Claim
86 words
An integrated circuit, operable in one of a plurality of operating modes, comprising: an input connection for receiving an input signal, the input signal is used to select the one of the plurality of operating modes; a first isolation circuit coupled to the input connection; a first latch circuit coupled to the first isolation circuit to volatilely store the input signal; a second isolation circuit coupled to the first latch circuit; and a second latch coupled to second isolation circuit to non-volatilely store the input signal.
Claim 12
Dependent Claim
19 words
The integrated circuit of claim 8 wherein the first latch circuit comprises a pair of cross coupled inverter circuits.
Claim 13
Dependent Claim
17 words
The integrated circuit of claim 8 wherein the second latch comprises at least one floating gate transistor.
Claim 14
Dependent Claim
17 words
The integrated circuit of claim 8 wherein first and second isolation circuits comprise a field effect transistor.
Claim 15
Dependent Claim
97 words
An integrated circuit, operable in one of a plurality of operating modes, comprising: first and second input connections for receiving an complementary input signals, the input signals are used to select the one of the plurality of operating modes a first isolation circuit coupled to the input connections to selectively isolate the first and second input connections from a first latch circuit to volatilely store the input signals; and a second isolation circuit coupled to the first latch circuit to selectively isolate the first latch circuit from a second latch circuit to non-volatilely store the input signals.
Claim 16
Dependent Claim
97 words
An integrated circuit, operable in one of a plurality of operating modes, comprising: first and second input connections for receiving an complementary input signals, the input signals are used to select the one of the plurality of operating modes a first isolation circuit coupled to the input connections to selectively isolate the first and second input connections from a first latch circuit to volatilely store the input signals; and a second isolation circuit coupled to the first latch circuit to selectively isolate the first latch circuit from a second latch circuit to non-volatilely store the input signals.
Claim 17
Dependent Claim
19 words
The integrated circuit of claim 12 wherein the first latch circuit comprises a pair of cross coupled inverter circuits.
Claim 18
Dependent Claim
15 words
The integrated circuit of claim 12 wherein the second latch comprises two floating gate transistors.
Claim 19
Dependent Claim
17 words
The integrated circuit of claim 12 wherein first and second isolation circuits comprise a field effect transistors.
Claim 20
Dependent Claim
182 words
An integrated circuit, operable in one of a plurality of operating modes, comprising: a first input connection coupled to receive a first input signal; a second input connection coupled to receive a second input signal, the second input signal is a complement of the first input signal; a first latch circuit to volatilely store the first and second input signals, the first latch circuit comprises a pair of cross coupled logic circuits and first and second inputs; a first isolation transistor coupled between the first input connection and the first input of the first latch circuit; a second isolation transistor coupled between the second input connection and the second input of the second latch circuit; a second latch circuit to non-volatilely store the first and second input signals, the second latch circuit comprising first and second floating gate transistors; a third isolation transistor coupled between the first input connection and the first floating gate transistor of the second latch circuit; and a fourth isolation transistor coupled between the second input connection and the second floating gate transistor of the second latch circuit.
Claim 21
Dependent Claim
182 words
An integrated circuit, operable in one of a plurality of operating modes, comprising: a first input connection coupled to receive a first input signal; a second input connection coupled to receive a second input signal, the second input signal is a complement of the first input signal; a first latch circuit to volatilely store the first and second input signals, the first latch circuit comprises a pair of cross coupled logic circuits and first and second inputs; a first isolation transistor coupled between the first input connection and the first input of the first latch circuit; a second isolation transistor coupled between the second input connection and the second input of the second latch circuit; a second latch circuit to non-volatilely store the first and second input signals, the second latch circuit comprising first and second floating gate transistors; a third isolation transistor coupled between the first input connection and the first floating gate transistor of the second latch circuit; and a fourth isolation transistor coupled between the second input connection and the second floating gate transistor of the second latch circuit.
Claim 22
Dependent Claim
42 words
The integrated circuit of claim 16 further comprising a comparator circuit, coupled to the first and second inputs and the first latch circuit, to compare the first and second input signals with data stored in either the first or second latch circuits.
References Cited (Backward Citations)
US4308627A
Cited
US4460982A
Cited
US4571704A
Cited
US4858185A
Cited
US5031142A
Cited
US5047664A
Cited
JPH03206709A
Cited
US5097449A
Cited
US5282990A
Cited
US5144159A
Cited
US5546561A
Cited
US5463757A
Cited
US5249158A
Cited
US5214316A
Cited
US5311470A
Cited
US5378936A
Cited
US5280447A
Cited
US5509134A
Cited
US5377199A
Cited
US5369754A
Cited
US5402370A
Cited
US5526364A
Cited
US5619453A
Cited
US5627784A
Cited
US5615159A
Cited
US5677885A
Cited
US5675540A
Cited
US5661690A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-31 | 2004-05-01 | 2004-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-31 | 2008-05-01 | 2008-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-31 | 2012-05-01 | 2012-10-31 | $7700.00 | Window Closed / Lapsed |