Semiconductor device and method for fabricating the same

Claim 2

A semiconductor device comprising: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a groove type element separation structure formed in the deep well region, one or more shallow well regions of a second conductivity type, formed in one or more island active regions surrounded by the groove type element separation structure; a source region and a drain region of the first conductivity type, and a contact region, respectively formed in a corresponding one of the one or more shallow well regions in a corresponding one of the one or more island active regions; a channel region formed between the source region and the drain region and adjacent to the contact region; a gate insulating film formed on the channel region; a gate electrode formed from above the gate insulating film to above the contact region, wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions at the contact region; wherein a portion of a periphery of the contact region is partially connected to the channel region, and a portion of the gate electrode on the contact region is extended to be over the groove type element separation structure.

Claim 3

A semiconductor device comprising: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a groove type element separation structure formed in the deep well region; one or more shallow well regions of a second conductivity type, formed in one or more island active regions surrounded by the groove type element separation structure; a source region and a drain region of the first conductivity type, and a contact region, respectively formed in a corresponding one of the one or more shallow well regions in a corresponding one of the one or more island active regions; a channel region formed between the source region and the drain region and adjacent to the contact region; a gate insulating film formed on the channel region; a gate electrode formed from above the gate insulating film to above the contact region, wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions at the contact region; wherein a second element separation region which is thicker than the gate insulating film is formed in a portion of the one or more island active regions and surrounding the contact region, a portion of a periphery of the contact region is partially connected to the channel region directly or via the second element separation region, and a portion of the gate electrode on the contact region is extended to be over the second element separation region or over the groove type element separation structure.

Claim 4

A semiconductor device comprising: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a groove type element separation structure formed in the deep well region; one or more shallow well regions of a second conductivity type, formed in one or more island active regions surrounded by the groove type element separation structure; a source region and a drain region of the first conductivity type, and a contact region, respectively formed in a corresponding one of the one or more shallow well regions in a corresponding one of the one or more island active regions; a channel region formed between the source region and the drain region and adjacent to the contact region; a gate insulating film formed on the channel region; a gate electrode formed from above the gate insulating film to above the contact region, wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions at the contact region; wherein a second element separation region which is thicker than the gate insulating film is formed in a portion of the one or more island active regions and surrounding the contact region, a portion of a periphery of the contact region is partially connected to the channel region directly or via the second element separation region, and a portion of the gate electrode on the contact region is extended to be over the second element separation region or over the groove type element separation structure.

Claim 5

A semiconductor device comprising: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a groove type element separation structure formed in the deep well region; one or more shallow well regions of a second conductivity type, formed in one or more island active regions surrounded by the groove type element separation structure; a source region and a drain region of the first conductivity type, and a contact region, respectively formed in a corresponding one of the one or more shallow well regions in a corresponding one of the one or more island active regions; a channel region formed between the source region and the drain region and adjacent to the contact region; a gate insulating film formed on the channel region; a gate electrode formed from above the gate insulating film to above the contact region, wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions at the contact region; wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions via one of a second source region and a second drain region of a second MOS transistor, and a constant voltage is applied to a gate electrode of the second MOS transistor.

Claim 6

A semiconductor device comprising: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a groove type element separation structure formed in the deep well region; one or more shallow well regions of a second conductivity type, formed in one or more island active regions surrounded by the groove type element separation structure; a source region and a drain region of the first conductivity type, and a contact region, respectively formed in a corresponding one of the one or more shallow well regions in a corresponding one of the one or more island active regions; a channel region formed between the source region and the drain region and adjacent to the contact region; a gate insulating film formed on the channel region; a gate electrode formed from above the gate insulating film to above the contact region, wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions at the contact region; wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions via one of a second source region and a second drain region of a second MOS transistor, and a constant voltage is applied to a gate electrode of the second MOS transistor.

Claim 7

A semiconductor device comprising: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a groove type element separation structure formed in the deep well region; one or more shallow well regions of a second conductivity type, formed in one or more island active regions surrounded by the groove type element separation structure; a source region and a drain region of the first conductivity type, and a contact region, respectively formed in a corresponding one of the one or more shallow well regions in a corresponding one of the one or more island active regions; a channel region formed between the source region and the drain region and adjacent to the contact region; a gate insulating film formed on the channel region; a gate electrode formed from above the gate insulating film to above the contact region, wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions at the contact region; wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions via one of a second source region and a second drain region of a second MOS transistor, and the drain region is connected to a second gate electrode of the second MOS transistor.

Claim 8

A semiconductor device comprising: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a groove type element separation structure formed in the deep well region; one or more shallow well regions of a second conductivity type, formed in one or more island active regions surrounded by the groove type element separation structure; a source region and a drain region of the first conductivity type, and a contact region, respectively formed in a corresponding one of the one or more shallow well regions in a corresponding one of the one or more island active regions; a channel region formed between the source region and the drain region and adjacent to the contact region; a gate insulating film formed on the channel region; a gate electrode formed from above the gate insulating film to above the contact region, wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions at the contact region; wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions via one of a second source region and a second drain region of a second MOS transistor, and the drain region is connected to a second gate electrode of the second MOS transistor.

Claim 9

A semiconductor device comprising: a semiconductor substrate; an n-type deep well region formed in the semiconductor substrate; a p-type deep well region formed in the semiconductor substrate; one or more p-type shallow well regions formed in the n-type deep well region; one or more n-type shallow well regions formed in the p-type deep well region; an N-channel MOS transistor respectively formed in the one or more p-type shallow well regions; and a P-channel MOS transistor respectively formed in the one or more n-type shallow well regions, wherein the N-channel MOS transistor includes an n-type source region and an n-type drain region formed in a corresponding one of the one or more p-type shallow well regions, a channel region formed between the n-type source region the n-type drain region, a contact region formed adjacent to the channel region and in the p-type shallow region, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film, wherein the P-channel MOS transistor includes a p-type source region and a p-type drain region formed in a corresponding one of the one or more n-type shallow well regions, a channel region formed between the p-type source region and the p-type drain region, a contact region formed adjacent to the channel region and in the n-type shallow well region, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film, and wherein the gate electrode of the N-channel MOS transistor is electrically connected to the p-type shallow well region, and the gate electrode of the P-channel MOS transistor is electrically connected to the n-type shallow well region.

Claim 10

A semiconductor device comprising: a semiconductor substrate; an n-type deep well region formed in the semiconductor substrate; a p-type deep well region formed in the semiconductor substrate; one or more p-type shallow well regions formed in the n-type deep well region; one or more n-type shallow well regions formed in the p-type deep well region; an N-channel MOS transistor respectively formed in the one or more p-type shallow well regions; and a P-channel MOS transistor respectively formed in the one or more n-type shallow well regions, wherein the N-channel MOS transistor includes an n-type source region and an n-type drain region formed in a corresponding one of the one or more p-type shallow well regions, a channel region formed between the n-type source region the n-type drain region, a contact region formed adjacent to the channel region and in the p-type shallow region, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film, wherein the P-channel MOS transistor includes a p-type source region and a p-type drain region formed in a corresponding one of the one or more n-type shallow well regions, a channel region formed between the p-type source region and the p-type drain region, a contact region formed adjacent to the channel region and in the n-type shallow well region, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film, and wherein the gate electrode of the N-channel MOS transistor is electrically connected to the p-type shallow well region, and the gate electrode of the P-channel MOS transistor is electrically connected to the n-type shallow well region.

Claim 11

A semiconductor device according to claim 5 , wherein the n-type deep well region is capable of functioning as an emitter or a collector of an npn type bipolar transistor; the one or more p-type shallow well regions are capable of functioning as a base of the npn type bipolar transistor; the n-type source region and the n-type drain region are capable of functioning as the collector or the emitter of the npn type bipolar transistor; the p-type deep well region is capable of functioning as an emitter or a collector of a pnp type bipolar transistor; the one or more n-type shallow well regions are capable of functioning as a base of the pnp bipolar transistor; the p-type source region and the p-type drain region are capable of functioning as the collector or the emitter of the pnp bipolar transistor.

Claim 12

A semiconductor device according to claim 6 , wherein the gate electrode of the N-channel MOS transistor is electrically connected to a corresponding one of the one or more p-type shallow well regions via source/drain regions of a first MOS transistor while the n-type drain region is electrically connected to a gate electrode of the first MOS transistor, the gate electrode of the P-channel MOS transistor is electrically connected to a corresponding one of the one or more n-type shallow well regions via source/drain regions of a second MOS transistor while the p-type drain region is electrically connected to a gate electrode of the second MOS transistor, and wherein the semiconductor device further comprises a p-type deeper well region which is deeper than the n-type deep well region, including the n-type deep well region, and an n-type deeper well region which is deeper than the p-type deep well region, including the p-type deep well region, a potential of the n-type deep well region and a potential of the p-type deeper well region are set to be identical to each other, and a potential of the p-type deep well region and a potential of the n-type deeper well region are set to be identical to each other.

Claim 13

A semiconductor device according to claim 5 , wherein adjacent one or more n-type shallow well regions or adjacent one or more p-type shallow well regions of adjacent elements are electrically separated from each other by a groove type element separation structure.

Claim 14

A semiconductor device according to claim 5 , wherein adjacent one or more n-type shallow well regions or adjacent one or more p-type shallow well regions of adjacent elements are electrically separated from each other by a groove type element separation structure and an impurity diffusion region which positions on a bottom of the groove type element separation structure and reaches the deep well region of an inverse conductivity type of the n-type or p-type one or more shallow well regions.

Claim 15

A semiconductor device according to claim 9 , further comprising: a second n-type well region surrounding the p-type deep well region, which is deeper than the p-type-deep well region; a second p-type well region surrounding the n-type deep well region, which is deeper than the n-type deep well region; and a groove type element separation structure for separating between the n-type deep well regions or between the p-type deep well regions or between the n-type deep well regions and the p-type deep well regions from each other.

Claim 16

A semiconductor device according to claim 5 , wherein the gate electrode of the P-channel or N-channel MOS transistor includes a polycrystalline silicon film formed on the gate insulating film and a metal silicide film formed on the polycrystalline silicon film, and wherein the metal silicide film is electrically connected to a corresponding one of the one or more n-type or p-type shallow well regions via the contact region of the corresponding one of the one or more n-type or p-type shallow well regions.

Claim 17

A semiconductor device according to claim 11 , wherein a high concentration impurity diffusion region, in which an impurity of the same conductivity type as that of the one or more n-type or p-type shallow well regions is diffused at a higher concentration than that of a reminder of the one or more n-type or p-type shallow well regions, is formed in the contact region, and an electrical connection is formed between the metal silicide film and the n-type or p-type shallow well region through the high concentration impurity diffusion region.

Claim 18

A semiconductor device according to claim 5 , further comprising an interlayer insulating film and an upper wiring provided on the interlayer insulating film, wherein a contact hole is formed in the interlayer insulating film, which penetrates through the gate electrode of the P-channel or N-channel MOS transistor and the gate insulating film so as to reach the contact region of the one or more n-type or p-type shallow well regions, wherein an electrical connection is formed between the upper wiring and the shallow well region on the bottom of the contact hole, and wherein an electrical connection is formed between the gate electrode and the upper wiring on a side wall region of the contact hole.

Claim 19

A semiconductor device according to claim 13 , wherein a high concentration impurity diffusion region, in which an impurity of the same conductivity type as that of the shallow well region is diffused at a higher concentration than that of a remainder of the shallow well region, is formed in the contact region.

Claim 20

A semiconductor device according to claim 5 , wherein the gate electrode is electrically connected to the shallow well region via one of a second source region and a second drain region of a second MOS transistor, and a constant voltage is applied to a gate electrode of the second MOS transistor.

Claim 21

A semiconductor device according to claim 5 , wherein the gate electrode is electrically connected to the shallow well region via one of a second source region and a second drain region of a second MOS transistor, and the drain region to connected to a second gate electrode of the second MOS transistor.

Claim 22

A semiconductor device according to claim 5 , wherein a junction between at least bottoms of the p-type or n-type source/drain regions, and the n-type or p-type shallow well region, is doped with nitrogen ions or carbon ions.

Claim 23

A semiconductor device according to claim 5 , wherein the contact region has a high impurity concentration of the same conductivity type as that of the one or more shallow well regions.

Claim 24

A semiconductor device comprising: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; one or more shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the one or more shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; a contact region formed adjacent to the channel region and in the shallow well region, and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions, and the one or more shallow wall regions is electrically separated from one or more adjacent shallow well regions, wherein the gate electrode includes a polycrystalline silicon film formed on the gate insulating firm and a metal silicide film formed on the polycrystalline silicon film, and wherein the metal silicide film is electrically connected to a corresponding one of the one or more shallow well regions via the contact region of the corresponding one of the one or more shallow well regions; wherein the silicide film formed on the surface of the contact region are directly contact with each other.

Claim 25

A semiconductor device comprising: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; one or more shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the one or more shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; a contact region formed adjacent to the channel region and in the shallow well region, and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the one or more shallow well regions, and the one or more shallow wall regions is electrically separated from one or more adjacent shallow well regions, wherein the gate electrode includes a polycrystalline silicon film formed on the gate insulating firm and a metal silicide film formed on the polycrystalline silicon film, and wherein the metal silicide film is electrically connected to a corresponding one of the one or more shallow well regions via the contact region of the corresponding one of the one or more shallow well regions; wherein the silicide film formed on the surface of the contact region are directly contact with each other.