Semiconductor integrated circuit device with latch up preventing structure

Claim 2

A semiconductor integrated circuit device comprising: a semiconductor region (21 or 42) of a first con­ductivity type (N or P); a source region (22 or 43) of a second conductivity type (P or N) formed in said semiconductor region (21 or 42) and directly connected to a first power source cir­cuit (VDD or GND) of the semiconductor integrated cir­cuit device; a drain region (23 or 43) of the second conduc­tivity type (P or N) formed adjacent to said source region (22 or 43) in said semiconductor region (21 or 42) and directly connected to a second power source cir­cuit (GND or VDD) of the semiconductor integrated cir­cuit device; and means (25, 27 or 46, 49) for connecting said first power source circuit (VDD or GND) to a base portion of a bipolar transistor structure (26 or 48) formed of said semiconductor region (21 or 42), source region (22 or 43), and drain region (23 or 44).

Claim 3

A device according to claim 1, further com­prising: a gate electrode (24 or 45) arranged over a channel region formed between said source region (22 or 43) and drain region (23 or 44) and connected to said first power source circuit (VDD or GND).

Claim 4

A device according to claim 1, characterized in that said bipolar transistor structure (26 or 48) is formed near the edge portion of a semiconductor chip (200) on which the semiconductor integrated circuit device is formed.

Claim 5

A device according to claim 1, characterized in that said bipolar transistor structure (26 or 48) is formed on the corner of a semiconductor chip (200) on which the semiconductor integrated circuit device is formed.

Claim 6

A device according to claim 1, characterized in that said bipolar transistor structure (48) is arranged by the side of a pad (12) connected to said first power source circuit (GND) of the semiconductor integrated circuit device.

Claim 7

A device according to claim 1, characterized in that the bipolar transistor structure (26) is arranged by the side of a pad (11) connected to said second power source circuit (VDD) of the semiconductor integrated circuit device.

Claim 8

A device according to claim 1, characterized in that said bipolar transistor structure (48) is arranged just under a pad (12) connected to said first power source circuit (GND) of the semiconductor integrated circuit device.

Claim 9

A device according to claim 1, characterized in that said bipolar transistor structure (26) is arranged just under a pad (11) connected to said second power source circuit (VDD) of the semiconductor integrated circuit device.

Claim 10

A semiconductor integrated circuit device com­prising: a semiconductor substrate (21) of a first con­ductivity type (N); a first source region (22) of a second conductivity type (P) formed in said semiconductor substrate (21) and connected to a first power source circuit (VDD) of the semiconductor integrated circuit device; a first drain region (23) of the second conduc­tivity type (P) formed adjacent to said first source region (22) in said semiconductor substrate (21) and connected to a second power source circuit (GND) of the semiconductor integrated circuit device; first connection means (25, 27) for connecting said first power source circuit (VDD) to a first base portion of a first bipolar transistor structure (26) formed of said semiconductor substrate (21), first source region (22), and first drain region (23); a well region (42) of the second conductivity type (P) formed in said semiconductor substrate (21); a second source region (43) of the first conduc­tivity type (N) formed in said well region (42) and con­nected to second power source circuit (GND) of the semiconductor integrated circuit device; a second drain region (44) of the first conductivity type (N) formed adjacent to said second source region (43) in said well region (42) and connected to the first power source circuit (VDD) of the semiconductor integrated circuit device; and second connection means (46, 49) for connecting said second power source circuit (GND) to a second base portion of a second bipolar transistor structure (48) formed of said well region (42), second source region (43), and second drain region (44).

Claim 11

A semiconductor integrated circuit device com­prising: a semiconductor substrate (21) of a first con­ductivity type (N); a first source region (22) of a second conductivity type (P) formed in said semiconductor substrate (21) and connected to a first power source circuit (VDD) of the semiconductor integrated circuit device; a first drain region (23) of the second conduc­tivity type (P) formed adjacent to said first source region (22) in said semiconductor substrate (21) and connected to a second power source circuit (GND) of the semiconductor integrated circuit device; first connection means (25, 27) for connecting said first power source circuit (VDD) to a first base portion of a first bipolar transistor structure (26) formed of said semiconductor substrate (21), first source region (22), and first drain region (23); a well region (42) of the second conductivity type (P) formed in said semiconductor substrate (21); a second source region (43) of the first conduc­tivity type (N) formed in said well region (42) and con­nected to second power source circuit (GND) of the semiconductor integrated circuit device; a second drain region (44) of the first conductivity type (N) formed adjacent to said second source region (43) in said well region (42) and connected to the first power source circuit (VDD) of the semiconductor integrated circuit device; and second connection means (46, 49) for connecting said second power source circuit (GND) to a second base portion of a second bipolar transistor structure (48) formed of said well region (42), second source region (43), and second drain region (44).

Claim 12

A device according to claim 9, further com­prising: a first gate electrode (24) arranged over a chan­nel region formed between said first source region (22) and first drain region (23) and connected to said first power source circuit (VDD).

Claim 13

A device according to claim 9, further com­prising: a second gate electrode (45) arranged over a chan­nel region formed between said second source region (43) and second drain region (44) and connected to said second power source circuit (GND).

Claim 14

A device according to claim 9, characterized in that said first bipolar transistor structure (26) is formed near the edge of one of four sides of a rec­tangular semiconductor chip (200) in which the semicon­ductor integrated circuit device is formed, and said second bipolar transistor structure (48) is formed near the edge of another one of the four sides of said rectangular semiconductor chip (200).

Claim 15

A device according to claim 9, characterized in that said first bipolar transistor structure (26) is formed on one of four corners of a rectangular semicon­ductor chip (200) in which the semiconductor integrated circuit device is formed, and said second bipolar tran­sistor structure (48) is formed on another one of the four corners of said rectangular semiconductor chip (200).

Claim 16

A semiconductor integrated circuit device comprising: a first node (N1) to which a first power source potential (VDD) is applied; a second node (N2) to which a second power source potential (GND) is applied; and a MOS transistor (13 or 14) having drain, source, and gate electrodes, wherein one of said source and drain electrodes is connected to said first node (N1), the other of said source and drain electrodes is con­nected to said second node (N2), and said gate electrode is connected to said source electrode.

Claim 17

A semiconductor integrated circuit device comprising: a first node (N1) to which a first power source potential (VDD) is applied; a second node (N2) to which a second power source potential (GND) is applied; and a MOS transistor (13 or 14) having drain, source, and gate electrodes, wherein one of said source and drain electrodes is connected to said first node (N1), the other of said source and drain electrodes is con­nected to said second node (N2), and said gate electrode is connected to said source electrode.

Claim 18

A semiconductor integrated circuit device according to claim 14, characterized in that the first power source potential (VDD) is a high potential, the second power source potential (GND) is a low potential, and said MOS transistor is a P channel MOS transistor (13).

Claim 19

A semiconductor integrated circuit device according to claim 14, characterized in that the first power source potential (VDD) is a low potential, the second power source potential (GND) is a high potential, and said MOS transistor is an N channel MOS transistor (14).

Claim 20

A semiconductor integrated circuit device comprising: a first node (N1) to which a first power source potential (VDD) is applied; a second node (N2) to which a second power source potential (GND) is applied; a P channel MOS transistor (13) having source and gate electrodes connected to said first node (N1) and a drain electrode connected to said second node (N2); and an N channel MOS transistor (14) having a drain electrode connected to said first node (N1) and source and gate electrodes connected to said second node (N2).

Claim 21

A semiconductor integrated circuit device comprising: a first node (N1) to which a first power source potential (VDD) is applied; a second node (N2) to which a second power source potential (GND) is applied; a P channel MOS transistor (13) having source and gate electrodes connected to said first node (N1) and a drain electrode connected to said second node (N2); and an N channel MOS transistor (14) having a drain electrode connected to said first node (N1) and source and gate electrodes connected to said second node (N2).