Semiconductor device having MOS transistor

Claim 2

A semiconductor device, comprising: a semiconductor region of a first conductivity type having a main surface; a pair of source/drain regions of a second conductivity type having a predetermined junction depth, formed spaced apart by a predetermined distance to sandwich a channel region on the main surface of said semiconductor region; first spaced apart implantation layers having a depth equal to or greater than the junction depth of said source/drain regions, formed along an entire junction region of said source/drain regions and including a material selected from the group consisting of nitrogen, fluorine, argon, oxygen and carbon; and a gate electrode formed on said channel region with a gate insulation layer posed therebetween.

Claim 3

The semiconductor device according to claim 1, wherein said first implantation layer has a depth greater than the junction depth of said source/drain regions and is formed to cover said source/drain regions.

Claim 4

The semiconductor device according to claim 1, wherein said gate electrode includes an impurity; and a second implantation layer including a material selected from the group consisting of nitrogen, fluorine, argon, oxygen and carbon is formed near a surface of said gate electrode at the side of said gate insulation layer.

Claim 5

The semiconductor device according to claim 3, wherein said impurity is of P type.

Claim 6

The semiconductor device according to claim 1, wherein said source/drain regions are of P-conductivity type.

Claim 7

A semiconductor device, comprising: a first semiconductor region of a first conductivity type having a main surface; a second semiconductor region of a second conductivity type having a main surface and formed adjacent to said first semiconductor region; a pair of first source/drain regions of a second conductivity type having a predetermined junction depth, formed spaced apart by a predetermined distance to sandwich a first channel region on the main surface of said first semiconductor region; first spaced apart implantation layers having a depth equal to or greater than the junction depth of said first source/drain regions, formed along an entire junction region of said first source/drain regions, and including a material selected from the group consisting of nitrogen, fluorine, argon, oxygen and carbon; a first gate electrode formed on said first channel region with a first gate insulation layer posed therebetween; a pair of second source/drain regions of a first conductivity type formed spaced apart by a predetermined distance to sandwich a second channel region on the main surface of said second semiconductor region; and a second gate electrode formed on said second channel region with a second gate insulation layer posed therebetween.

Claim 8

A semiconductor device, comprising: a first semiconductor region of a first conductivity type having a main surface; a second semiconductor region of a second conductivity type having a main surface and formed adjacent to said first semiconductor region; a pair of first source/drain regions of a second conductivity type having a predetermined junction depth, formed spaced apart by a predetermined distance to sandwich a first channel region on the main surface of said first semiconductor region; first spaced apart implantation layers having a depth equal to or greater than the junction depth of said first source/drain regions, formed along an entire junction region of said first source/drain regions, and including a material selected from the group consisting of nitrogen, fluorine, argon, oxygen and carbon; a first gate electrode formed on said first channel region with a first gate insulation layer posed therebetween; a pair of second source/drain regions of a first conductivity type formed spaced apart by a predetermined distance to sandwich a second channel region on the main surface of said second semiconductor region; and a second gate electrode formed on said second channel region with a second gate insulation layer posed therebetween.

Claim 9

The semiconductor device according to claim 6, wherein said first and second gate electrodes include an impurity of a second conductivity type; a second implantation layer including a material selected from the group consisting of nitrogen, fluorine, argon, oxygen and carbon is formed near a surface of said first and second gate electrodes at the side of said first and second gate insulation layers.

Claim 10

The semiconductor device according to claim 6, wherein said first implantation layer is formed to have a depth greater than the junction depth of said first source/drain regions and to cover said first source/drain regions.