Patent US6544874B2 successfully refreshed from Google Patents.
US6544874B2
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Method for forming junction on insulator (JOI) structure
Assignee: International Business Machines Corp
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Filing: 2001-08-13
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Granted: 2003-04-08
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Expires: 2021-08-13
Abstract
Abstract A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.
Inventors
- 👤 Jack A. Mandelman
- 👤 Kevin K. Chan
- 👤 Bomy A. Chen
- 👤 Oleg Gluschenkov
- 👤 Rajarao Jammy
- 👤 Victor Ku
- 👤 Chung H. Lam
- 👤 Nivo Rovedo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:52
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D86/00; H10D86/01; H10D86/201; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10D84/0123; H10D84/0126; H10D84/0151
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
120 words
A method of fabricating a junction on insulator (JOI) structure comprising the steps of: (a) selectively recessing portions of a semiconductor substrate that abut one or more gate stack regions, while not recessing other portions of said semiconductor substrate that contain well contacts; (b) forming an insulating layer on at least said recessed portions of said semiconductor substrate; (c) filling said recessed portions of said semiconductor substrate with a conductive material and planarizing to a top surface of said one or more gate stack regions; (d) recessing a portion of said conductive material abutting said one or more gate stack regions, wherein said recessing stops above said insulating layer; and (e) removing said insulating layer from over said well contacts.
Claim 2
Independent Claim
120 words
A method of fabricating a junction on insulator (JOI) structure comprising the steps of: (a) selectively recessing portions of a semiconductor substrate that abut one or more gate stack regions, while not recessing other portions of said semiconductor substrate that contain well contacts; (b) forming an insulating layer on at least said recessed portions of said semiconductor substrate; (c) filling said recessed portions of said semiconductor substrate with a conductive material and planarizing to a top surface of said one or more gate stack regions; (d) recessing a portion of said conductive material abutting said one or more gate stack regions, wherein said recessing stops above said insulating layer; and (e) removing said insulating layer from over said well contacts.
Claim 3
Dependent Claim
28 words
The method of claim 1 wherein said semiconductor substrate comprises a semiconductor material selected from the group consisting of Si, Ge, SiGe, GaAs, InAs, InP, Si/Si and Si/SiGe.
Claim 4
Dependent Claim
11 words
The method of claim 1 wherein said semiconductor substrate comprises Si.
Claim 5
Dependent Claim
23 words
The method of claim 1 wherein said well contact regions are abutted by isolation regions that are also formed in said semiconductor substrate.
Claim 6
Dependent Claim
20 words
The method of claim 4 wherein said isolation regions are shallow trench isolation regions or local oxidation of silicon regions.
Claim 7
Dependent Claim
51 words
The method of claim 1 wherein said one or more patterned gate stack regions comprise at least a gate dielectric formed atop a surface of said semiconductor substrate; a gate conductor formed atop said gate dielectric; and insulating spacers formed on exposed vertical sidewalls of said gate dielectric and gate conductor.
Claim 8
Dependent Claim
16 words
The method of claim 6 further comprising a dielectric capping layer formed atop said gate conductor.
Claim 9
Dependent Claim
16 words
The method of claim 6 wherein said dielectric capping layer is removed after performing step (e).
Claim 10
Dependent Claim
18 words
The method of claim 8 wherein said dielectric capping layer is removed by a reactive ion etching process.
Claim 11
Dependent Claim
27 words
The method of claim 1 wherein step (a) comprising the steps of forming a mask over the well contacts and etching exposed surfaces of said semiconductor substrate.
Claim 12
Dependent Claim
12 words
The method of claim 10 wherein said etching comprises reactive ion etching.
Claim 13
Dependent Claim
22 words
The method of claim 11 wherein said reactive ion etching includes the use of a plasma containing HBr and Cl 2 .
Claim 14
Dependent Claim
22 words
The method of claim 1 wherein said insulating layer is composed of an oxide, nitride, oxynitride or any combination and mutilayers thereof.
Claim 15
Dependent Claim
14 words
The method of claim 13 wherein said insulating layer is composed of an oxide.
Claim 16
Dependent Claim
14 words
The method of claim 14 wherein said oxide is a high-density plasma deposited oxide.
Claim 17
Dependent Claim
20 words
The method of claim 1 wherein said insulating layer is formed by a deposition process or a thermal growing process.
Claim 18
Dependent Claim
22 words
The method of claim 1 wherein step (a) includes forming said insulating layer on vertical surfaces that surround said gate stack regions.
Claim 19
Dependent Claim
21 words
The method of claim 17 wherein said insulating layer is selectively removed from said vertical surfaces prior to performing step (c).
Claim 20
Dependent Claim
21 words
The method of claim 18 wherein said insulating layer is removed from said vertical surfaces by a selective isotropic etching process.
Claim 21
Dependent Claim
21 words
The method of claim 19 wherein said selective isotropic etching process includes the use of dilute HF as a chemical etchant.
Claim 22
Dependent Claim
20 words
The method of claim 1 wherein said insulating layer has a thickness of from about 20 to about 200 nm.
Claim 23
Dependent Claim
20 words
The method of claim 21 wherein said insulating layer has a thickness of from about 50 to about 100 nm.
Claim 24
Dependent Claim
13 words
The method of claim 1 wherein said filling step comprises a deposition process.
Claim 25
Dependent Claim
41 words
The method of claim 1 wherein said conductive material comprises polysilicon, amorphous Si, a conductive elemental metal, alloys of a conductive elemental metal, suicides of a conductive elemental metal, nitrides of a conductive elemental metal or any combination and multilayers thereof.
Claim 26
Dependent Claim
14 words
The method of claim 24 wherein said conductive material is polysilicon or amorphous Si.
Claim 27
Dependent Claim
14 words
The method of claim 1 wherein said planarizing step includes chemical-mechanical polishing or grinding.
Claim 28
Dependent Claim
14 words
The method of claim 1 wherein step (d) comprises a reactive ion etching process.
Claim 29
Dependent Claim
22 words
The method of claim 27 wherein said reactive ion etching includes the use of a plasma comprising HBr and Cl 2 .
Claim 30
Dependent Claim
14 words
The method of claim 1 wherein step (e) comprises a chemical wet etching process.
Claim 31
Dependent Claim
17 words
The method of claim 29 wherein said chemical wet etching process includes the use of dilute HF.
Claim 32
Independent Claim
138 words
A method of fabricating a junction on insulator (JOI) structure comprising the steps of: (a) selectively recessing portions of a semiconductor substrate that abut one or more gate stack regions, while not recessing other portions of said semiconductor substrate that contain well contacts; (b) forming an insulating layer on at least said recessed portions of said semiconductor substrate; (c) filling said recessed portions of said semiconductor substrate with polysilicon or amorphous Si and planarizing to a top surface of said one or more gate stack regions; (d) recessing a portion of said polysilicon or amorphous Si abutting said one or more gate stack regions, wherein said recessing stops above said insulating layer; (e) removing said insulating layer from over said well contacts; and (f) forming source/drain diffusion regions in said recessed portion of said polysilicon or amorphous Si.
Claim 33
Independent Claim
138 words
A method of fabricating a junction on insulator (JOI) structure comprising the steps of: (a) selectively recessing portions of a semiconductor substrate that abut one or more gate stack regions, while not recessing other portions of said semiconductor substrate that contain well contacts; (b) forming an insulating layer on at least said recessed portions of said semiconductor substrate; (c) filling said recessed portions of said semiconductor substrate with polysilicon or amorphous Si and planarizing to a top surface of said one or more gate stack regions; (d) recessing a portion of said polysilicon or amorphous Si abutting said one or more gate stack regions, wherein said recessing stops above said insulating layer; (e) removing said insulating layer from over said well contacts; and (f) forming source/drain diffusion regions in said recessed portion of said polysilicon or amorphous Si.
Claim 34
Dependent Claim
25 words
The method of claim 31 wherein said source/drain diffusion regions are formed by ion implantation, gas phase doping, solid source doping or plasma immersion doping.
Claim 35
Independent Claim
157 words
A method of fabricating a junction on insulator (JOI) structure comprising the steps of: (a) selectively recessing portions of a semiconductor substrate that abut one or more gate stack regions, while not recessing other portions of said semiconductor substrate that contain well contacts, wherein said one or more gate stack regions include disposable spacers formed atop insulating spacers that are formed on exposed vertical sidewalls of each of said one or more gate stack regions; (b) removing said disposable spacers; (c) forming an insulating layer on at least said recessed portions of said semiconductor substrate; (d) filling said recessed portions of said semiconductor substrate with a conductive material and planarizing to a top surface of said one or more gate stack regions; (e) recessing a portion of said conductive material abutting said one or more gate stack regions, wherein said recessing stops above said insulating layer; and (f) removing said insulating layer from over said well contacts.
Claim 36
Independent Claim
157 words
A method of fabricating a junction on insulator (JOI) structure comprising the steps of: (a) selectively recessing portions of a semiconductor substrate that abut one or more gate stack regions, while not recessing other portions of said semiconductor substrate that contain well contacts, wherein said one or more gate stack regions include disposable spacers formed atop insulating spacers that are formed on exposed vertical sidewalls of each of said one or more gate stack regions; (b) removing said disposable spacers; (c) forming an insulating layer on at least said recessed portions of said semiconductor substrate; (d) filling said recessed portions of said semiconductor substrate with a conductive material and planarizing to a top surface of said one or more gate stack regions; (e) recessing a portion of said conductive material abutting said one or more gate stack regions, wherein said recessing stops above said insulating layer; and (f) removing said insulating layer from over said well contacts.
Claim 37
Dependent Claim
14 words
The method of claim 33 wherein said conductive material comprises polysilicon or amorphous Si.
Claim 38
Dependent Claim
21 words
The method of claim 34 further comprising forming source/drain diffusion regions in said recessed portion of said polysilicon or amorphous Si.
Claim 39
Independent Claim
135 words
A method of fabricating a junction on insulator (JOI) structure comprising the steps of: (a) selectively recessing portions of a Si substrate that abut one or more gate stack. regions, while not recessing other portions of said Si substrate that contain well contacts; (b) forming a high-density plasma oxide layer on at least said recessed portions of said Si substrate; (c) filling said recessed portions of said Si substrate with polysilicon and planarizing to a top surface of said one or more gate stack regions; (d) recessing a portion of said polysilicon abutting said one or more gate stack regions, wherein said recessing stops above said high-density plasma oxide layer; (e) removing said high-density plasma oxide layer from over said well contacts; and (f) forming source/drain diffusion regions in said recessed portion of said polysilicon.
Claim 40
Independent Claim
135 words
A method of fabricating a junction on insulator (JOI) structure comprising the steps of: (a) selectively recessing portions of a Si substrate that abut one or more gate stack. regions, while not recessing other portions of said Si substrate that contain well contacts; (b) forming a high-density plasma oxide layer on at least said recessed portions of said Si substrate; (c) filling said recessed portions of said Si substrate with polysilicon and planarizing to a top surface of said one or more gate stack regions; (d) recessing a portion of said polysilicon abutting said one or more gate stack regions, wherein said recessing stops above said high-density plasma oxide layer; (e) removing said high-density plasma oxide layer from over said well contacts; and (f) forming source/drain diffusion regions in said recessed portion of said polysilicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-04-07 | 2006-10-07 | 2007-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-04-07 | 2010-10-07 | 2011-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-04-07 | 2014-10-07 | 2015-04-08 | $7700.00 | Window Closed / Lapsed |