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US6515913B2 Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor memory device and defect remedying method thereof

Assignee: Hitachi Ltd
•
Filing: 2001-12-04
•
Granted: 2003-02-04
•
Expires: 2021-12-04
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Abstract

Abstract Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Inventors

  • 👤 Kazuhiko Kajigaya
  • 👤 Kazuyuki Miyazawa
  • 👤 Manabu Tsunozaki
  • 👤 Kazuyoshi Oshima
  • 👤 Takashi Yamazaki
  • 👤 Yuji Sakai
  • 👤 Jiro Sawada
  • 👤 Yasunori Yamaguchi
  • 👤 Tetsurou Matsumoto
  • 👤 Shinji Udo
  • 👤 Hiroshi Yoshioka
  • 👤 Hirokazu Saito
  • 👤 Mitsuhiro Takano
  • 👤 Makoto Morino
  • 👤 Sinichi Miyatake
  • 👤 Eiji Miyamoto
  • 👤 Yasuhiro Kasama
  • 👤 Akira Endo
  • 👤 Ryoichi Hori
  • 👤 Jun Etoh
  • 👤 Masashi Horiguchi
  • 👤 Shinichi Ikenaga
  • 👤 Atsushi Kumata

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 12:55
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C29/00; G11C29/04; G11C29/06; G11C29/08; G11C29/12; G11C29/12005; G11C29/12015; G11C29/18; G11C29/24; G11C29/30; G11C29/34; G11C29/50; G11C29/50012; G11C29/70; G11C29/78; G11C29/80; G11C29/804; G11C29/83; G11C29/832; G11C29/84; G11C29/844; G11C5/00; G11C5/02; G11C5/025; G11C5/04; G11C5/06; G11C5/063; H10B; H10B12/00; H10B12/50; H10D; H10D84/00; H10D84/90; H10D84/998; H10D89/00; H10D89/10; G11C29/26; G11C2029/2602; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/551; H10W72/552; H10W72/5522; H10W72/59; H10W72/851; H10W72/853; H10W72/865; H10W72/931; H10W72/932; H10W72/934; H10W72/951; H10W72/952; H10W74/00; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/754; H10W90/756

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 111 words
A semiconductor storage device comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers connected to said plurality of bit lines, wherein the number of row address bits x used for selecting one or more of said plurality of word lines is larger than the number of column address bits, wherein the number of activated sense amplifiers per one memory access is expressed am n/2 x , wherein N bits obtained through said activated sense amplifiers are output as data, and wherein N is one of numbers in a progression expressed as 2 k , k=2, 3, 4.
Claim 2
Dependent Claim 111 words
A semiconductor storage device comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers connected to said plurality of bit lines, wherein the number of row address bits x used for selecting one or more of said plurality of word lines is larger than the number of column address bits, wherein the number of activated sense amplifiers per one memory access is expressed am n/2 x , wherein N bits obtained through said activated sense amplifiers are output as data, and wherein N is one of numbers in a progression expressed as 2 k , k=2, 3, 4.
Claim 3
Dependent Claim 117 words
A semiconductor storage device comprising: a plurality of word lines: a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers, wherein the number of row address bits x used for selecting one or more of said plurality of word lines is larger than the number of column address bits y, wherein the number of activated sense amplifiers per one memory access is expressed as n/2 x , wherein N bits obtained through said activated sense amplifiers are output as data, wherein N is one of numbers in a progression expressed as 2 k , k=2, 3, 4,- - -, and wherein n is expressed an n=2 x· 2 y· N.
Claim 4
Dependent Claim 117 words
A semiconductor storage device comprising: a plurality of word lines: a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers, wherein the number of row address bits x used for selecting one or more of said plurality of word lines is larger than the number of column address bits y, wherein the number of activated sense amplifiers per one memory access is expressed as n/2 x , wherein N bits obtained through said activated sense amplifiers are output as data, wherein N is one of numbers in a progression expressed as 2 k , k=2, 3, 4,- - -, and wherein n is expressed an n=2 x· 2 y· N.
Claim 5
Dependent Claim 141 words
A semiconductor storage device comprising: a plurality of word lines: a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers, wherein the number of row address bits x used for selecting one or more of said plurality of word lines is larger than the number of column address bits, wherein the number of activated sense amplifiers per one memory access is expressed as n/2 x , wherein N bits obtained through said activated sense amplifiers are output as data, wherein N is one of numbers in a progression expressed as 2 k , k= 2, 3, 4,- - -, wherein each of said memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor, and wherein said n bits are 16 megabits or more.
Claim 6
Dependent Claim 141 words
A semiconductor storage device comprising: a plurality of word lines: a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers, wherein the number of row address bits x used for selecting one or more of said plurality of word lines is larger than the number of column address bits, wherein the number of activated sense amplifiers per one memory access is expressed as n/2 x , wherein N bits obtained through said activated sense amplifiers are output as data, wherein N is one of numbers in a progression expressed as 2 k , k= 2, 3, 4,- - -, wherein each of said memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor, and wherein said n bits are 16 megabits or more.
Claim 7
Dependent Claim 127 words
A semiconductor storage device comprising: a plurality of word lines: a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers, wherein the number of row address bits x used for selecting one or more of said plurality of word lines is larger than the number of column address bits y, wherein the number of activated sense amplifiers per one memory access is expressed as n/2 x , wherein N bits obtained through said activated sense amplifiers are output as data, wherein N is one of numbers in a progression expressed as 2 k , k=2, 3, 4,- - -, and wherein the value of N can be changed by changing the value of y without changing the value of x.
Claim 8
Dependent Claim 127 words
A semiconductor storage device comprising: a plurality of word lines: a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers, wherein the number of row address bits x used for selecting one or more of said plurality of word lines is larger than the number of column address bits y, wherein the number of activated sense amplifiers per one memory access is expressed as n/2 x , wherein N bits obtained through said activated sense amplifiers are output as data, wherein N is one of numbers in a progression expressed as 2 k , k=2, 3, 4,- - -, and wherein the value of N can be changed by changing the value of y without changing the value of x.
Claim 9
Dependent Claim 127 words
A semiconductor storage device comprising: a plurality of word lines: a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers, wherein the number of row address bits x used for selecting one or more of said plurality of word lines is larger than the number of column address bits y, wherein the number of activated sense amplifiers per one memory access is expressed as n/2 x , wherein N bits obtained through said activated sense amplifiers are output as data, wherein N is one of numbers in a progression expressed as 2 k , k=2, 3, 4,- - -, and wherein the value of N can be changed by changing the value of y without changing the value of x.
Claim 10
Dependent Claim 127 words
A semiconductor storage device comprising: a plurality of word lines: a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers, wherein the number of row address bits x used for selecting one or more of said plurality of word lines is larger than the number of column address bits y, wherein the number of activated sense amplifiers per one memory access is expressed as n/2 x , wherein N bits obtained through said activated sense amplifiers are output as data, wherein N is one of numbers in a progression expressed as 2 k , k=2, 3, 4,- - -, and wherein the value of N can be changed by changing the value of y without changing the value of x.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2006-02-03 2006-08-05 2007-02-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2010-02-03 2010-08-05 2011-02-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2014-02-03 2014-08-05 2015-02-04 $7700.00 Window Closed / Lapsed

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