Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines; a redundant memory cell array having either a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines, or a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; and a redundancy saving circuit including either one or more row redundancy array saving bit lines for saving one or more bit-line faults occurring in the row redundancy array or one or more column redundancy array saving word lines for saving one or more word-line faults occurring in the column redundancy array.

Claim 3

The semiconductor memory device as claimed in claim 1, further comprising means for selecting said one or more row redundancy array saving bit lines from an address signal given to the redundant word lines.

Claim 4

The semiconductor memory device as claimed in claim 1, further comprising means for selecting said one or more column redundancy array saving word lines from an address signal given to the redundant bit lines.

Claim 5

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines; a redundant memory cell array having either a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines, or a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; and a redundancy saving circuit for saving one or more bit-line faults occurring in the row redundancy array or for saving one or more word-line faults occurring in the column redundancy array, wherein the memory cells array comprises a plurality of blocks; and the semiconductor memory device comprises means for selecting one of the redundant word lines from a block address for selecting one of the blocks and a row address for selecting one of the word lines of the memory cell array and for selecting said one or more column redundancy array saving word lines from at least one of the block address and the row address.

Claim 6

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines; a redundant memory cell array having either a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines, or a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; and a redundancy saving circuit for saving one or more bit-line faults occurring in the row redundancy array or for saving one or more word-line faults occurring in the column redundancy array, wherein the memory cells array comprises a plurality of blocks; and the semiconductor memory device comprises means for selecting one of the redundant word lines from a block address for selecting one of the blocks and a row address for selecting one of the word lines of the memory cell array and for selecting said one or more column redundancy array saving word lines from at least one of the block address and the row address.

Claim 7

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines: a redundant memory cell array having either a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines, or a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; and a redundancy saving circuit for saving one or more bit-line faults occurring in the row redundancy array or for saving one or more word-line faults occurring in the column redundancy array, wherein the memory cell array comprises a plurality of blocks; and the semiconductor memory device comprises means for selecting one of the redundant bit lines from a block address for selecting one of the blocks and a column address for selecting one of the bit lines of the memory cell array and for selecting said one or more row redundancy array saving bit lines from at least one of the block address and the column address.

Claim 8

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines: a redundant memory cell array having either a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines, or a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; and a redundancy saving circuit for saving one or more bit-line faults occurring in the row redundancy array or for saving one or more word-line faults occurring in the column redundancy array, wherein the memory cell array comprises a plurality of blocks; and the semiconductor memory device comprises means for selecting one of the redundant bit lines from a block address for selecting one of the blocks and a column address for selecting one of the bit lines of the memory cell array and for selecting said one or more row redundancy array saving bit lines from at least one of the block address and the column address.

Claim 9

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines; a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines; a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; a row redundancy array saving bit line circuit having one or more row redundancy array saving bit lines for saving one or more bit-line faults occurring in the row redundancy array; and a column redundancy array saving word line circuit having one or more column redundancy array saving word lines for saving one or more word-line faults occurring in the column redundancy array.

Claim 10

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines; a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines; a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; a row redundancy array saving bit line circuit having one or more row redundancy array saving bit lines for saving one or more bit-line faults occurring in the row redundancy array; and a column redundancy array saving word line circuit having one or more column redundancy array saving word lines for saving one or more word-line faults occurring in the column redundancy array.

Claim 11

The semiconductor memory device as claimed in claim 6, further comprising: first means for selecting said one or more row redundancy array saving bit lines from an address signal given to the redundant word lines; and second means for selecting said one or more column redundancy array saving word lines from an address signal given to the redundant bit lines.

Claim 12

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines: a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines; a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; a row redundancy array saving bit line circuit for saving one or more bit-line faults occurring in the row redundancy array; and a column redundancy array saving word line circuit for saving one or more word-line faults occurring in the column redundancy array, wherein the memory cell array comprises a plurality of blocks; and wherein the semiconductor memory device comprises first means for selecting one of the redundant word lines from a block address for selecting one of the blocks and a row address for selecting one of the word lines of the memory cell array and for selecting said one or more column redundancy array saving word lines from at least one of the block address and the row address; and second means for selecting one of the redundant bit lines from the block address for selecting one of the blocks and a column address for selecting one of the bit lines of the memory cell array and for selecting said one or more redundancy array saving word lines from at least one of the block address and the column address.

Claim 13

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines: a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines; a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; a row redundancy array saving bit line circuit for saving one or more bit-line faults occurring in the row redundancy array; and a column redundancy array saving word line circuit for saving one or more word-line faults occurring in the column redundancy array, wherein the memory cell array comprises a plurality of blocks; and wherein the semiconductor memory device comprises first means for selecting one of the redundant word lines from a block address for selecting one of the blocks and a row address for selecting one of the word lines of the memory cell array and for selecting said one or more column redundancy array saving word lines from at least one of the block address and the row address; and second means for selecting one of the redundant bit lines from the block address for selecting one of the blocks and a column address for selecting one of the bit lines of the memory cell array and for selecting said one or more redundancy array saving word lines from at least one of the block address and the column address.

Claim 14

The semiconductor memory device as claimed in claim 8, wherein: said first means comprises means for storing first information regarding whether or not the column redundancy array should be saved and for selecting said one or more column redundancy array saving word lines from at least one of the block address and the row address when said first information shows that the column redundancy array should be saved; and said second means comprises means for storing second information regarding whether or not the row redundancy array should be saved and for selecting said one or more row redundancy array saving bit lines from at least one of the block address and the column address when said second information shows that the row redundancy array should be saved.

Claim 15

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines; a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines; a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; a row redundancy array saving bit line circuit for saving one or more bit-line faults occurring in the row redundancy array; and a column redundancy array saving word line circuit for saving one or more word-line faults occurring in the column redundancy array, wherein the block address is grouped into a first group and a second group; and wherein said semiconductor memory device further comprises first means for selecting, for one or more faulty word lines in the memory cell array, one or more redundant word lines of said row redundancy array from the first group of the block address; and wherein said second means comprises means for selecting, for one or more faulty bit lines in the memory cell array, one or more redundant bit lines of said column redundancy array from the second group of the block address.

Claim 16

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines; a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines; a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; a row redundancy array saving bit line circuit for saving one or more bit-line faults occurring in the row redundancy array; and a column redundancy array saving word line circuit for saving one or more word-line faults occurring in the column redundancy array, wherein the block address is grouped into a first group and a second group; and wherein said semiconductor memory device further comprises first means for selecting, for one or more faulty word lines in the memory cell array, one or more redundant word lines of said row redundancy array from the first group of the block address; and wherein said second means comprises means for selecting, for one or more faulty bit lines in the memory cell array, one or more redundant bit lines of said column redundancy array from the second group of the block address.

Claim 17

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines: a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines; a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; a row redundancy array saving bit line circuit for saving one or more bit-line faults occurring in the row redundancy array; and a column redundancy array saving word line circuit for saving one or more word-line faults occurring in the column redundancy array; first means for selecting said one or more row redundancy array saving bit lines from an address signal given to the redundant word lines; and second means for selecting said one or more column redundancy array saving word lines from an address signal given to the redundant bit lines, wherein the row redundancy array saving bit line circuit comprises one or more row redundancy array saving bit lines for each block of a plurality of blocks, said each block being defined for the row address; and the column redundancy array saving word line circuit comprises one or more column redundancy array saving word lines for said each block, said each block being defined for the column address.

Claim 18

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines: a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines; a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; a row redundancy array saving bit line circuit for saving one or more bit-line faults occurring in the row redundancy array; and a column redundancy array saving word line circuit for saving one or more word-line faults occurring in the column redundancy array; first means for selecting said one or more row redundancy array saving bit lines from an address signal given to the redundant word lines; and second means for selecting said one or more column redundancy array saving word lines from an address signal given to the redundant bit lines, wherein the row redundancy array saving bit line circuit comprises one or more row redundancy array saving bit lines for each block of a plurality of blocks, said each block being defined for the row address; and the column redundancy array saving word line circuit comprises one or more column redundancy array saving word lines for said each block, said each block being defined for the column address.

Claim 19

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines; a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines; a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; a row redundancy array saving bit line circuit for saving one or more bit-line faults occurring in the row redundancy array; and a column redundancy array saving word line circuit for saving one or more word-line faults occurring in the column redundancy array; first means for selecting said one or more row redundancy array saving bit lines from an address signal given to redundant word lines; and second means for selecting said one or more column redundancy array saving word lines from an address signal given to the redundant bit lines, wherein a switching circuit selecting one of the memory cell array, the row redundancy circuit and the column redundancy circuit in order to receive data from an outside of the semiconductor memory device and transmit data to the outside thereof.

Claim 20

A semiconductor memory device comprising: a memory cell array having memory cells connected to word lines and bit lines; a row redundancy array which is commonly provided to the memory cells and has redundant word lines for saving faulty word lines; a column redundancy array which is commonly provided to the memory cells and has redundant bit lines for saving faulty bit lines; a row redundancy array saving bit line circuit for saving one or more bit-line faults occurring in the row redundancy array; and a column redundancy array saving word line circuit for saving one or more word-line faults occurring in the column redundancy array; first means for selecting said one or more row redundancy array saving bit lines from an address signal given to redundant word lines; and second means for selecting said one or more column redundancy array saving word lines from an address signal given to the redundant bit lines, wherein a switching circuit selecting one of the memory cell array, the row redundancy circuit and the column redundancy circuit in order to receive data from an outside of the semiconductor memory device and transmit data to the outside thereof.