Priority encoded spare element decoder

Claim 2

In a memory array formed on a semiconductor chip comprising memory cells arranged in rows and columns, some of the rows being standard rows and N of the rows being initially spares to be substituted for standard rows which include defective cells, where N is an integer equal to or greater than 2; the improvement comprising: means for selectively substituting any one of said N spare rows for any one of said standard rows including means for encoding the spare rows in a predetermined order of priority and selectively substituting a spare row of higher priority for a spare row of lower priority.

Claim 3

In a memory array formed on a semiconductor chip comprising memory cells arranged in rows and columns, some of the rows being standard rows and N of the rows being initially spares to be substituted for standard rows which include defective cells, where N is an integer equal to or greater than 2; the improvement comprising: permanently programmable means for selectively substituting any one of said N spare rows for any one of said standard rows including means encoding the spare rows in a predetermined order of priority for selectively substituting a spare row of higher priority for a defective spare row of lower priority.

Claim 4

In a memory array formed on a semiconductor chip comprising memory cells arranged in rows and columns, some of the rows being standard rows and N of the rows being initially spares to be substituted for standard rows which include defective cells, where N is an integer equal to or greater than 2; the improvement comprising: permanently programmable means for selectively substituting any one of said N spare rows for any one of said standard rows including means encoding the spare rows in a predetermined order of priority for selectively substituting a spare row of higher priority for a defective spare row of lower priority.

Claim 5

The improvement as claimed in claim 2, wherein said means encoding the spare rows includes N inputs and N outputs, each input corresponding to an output, and each output corresponding to a different one of said N spare rows; said means encoding the spare rows including means arranging its N inputs in an order of priority from 1 to N for enabling only the one of its outputs at any one time corresponding to the highest priority input to which an enabled signal is applied.

Claim 6

The improvement as claimed in claim 3 wherein said permanently programmable means is responsive to incoming addresses and includes permanently programmed means for applying enabling signals to selected ones of said N inputs of said encoding means whenever an incoming address matches a previously programmed address.

Claim 7

A monolithic integrated circuit comprising: a standard memory array of cells arranged in rows and columns, with a row conductor per row of cells and a column conductor per column of cells; a row decoder and a column decoder; means coupling the row decoder to the row conductors; means coupling the column decoder to the column conductors; N spare rows of cells each spare row having the same number of columns as said standard array; where N is an integer equal to or greater than 2; a spare row programmable means having N outputs, one output per spare row, said programmable means being responsive to incoming addresses and being selectively programmed to produce enabling signals at preselected outputs whenever the incoming address matches a previously programmed address; encoded decoder means having N inputs, each input being connected to a different one of the N outputs of said programmable means, and having N outputs one output per spare row; said decoder means including means for encoding its N inputs in an order of priority from 1 to N for enabling only that one of its N outputs corresponding to its enabled input having the highest priority; and means for coupling each one of said N decoder means outputs to a different one of said N spare rows.

Claim 8

A monolithic integrated circuit comprising: a standard memory array of cells arranged in rows and columns, with a row conductor per row of cells and a column conductor per column of cells; a row decoder and a column decoder; means coupling the row decoder to the row conductors; means coupling the column decoder to the column conductors; N spare rows of cells each spare row having the same number of columns as said standard array; where N is an integer equal to or greater than 2; a spare row programmable means having N outputs, one output per spare row, said programmable means being responsive to incoming addresses and being selectively programmed to produce enabling signals at preselected outputs whenever the incoming address matches a previously programmed address; encoded decoder means having N inputs, each input being connected to a different one of the N outputs of said programmable means, and having N outputs one output per spare row; said decoder means including means for encoding its N inputs in an order of priority from 1 to N for enabling only that one of its N outputs corresponding to its enabled input having the highest priority; and means for coupling each one of said N decoder means outputs to a different one of said N spare rows.

Claim 9

The combination as claimed in claim 5 wherein said programmable means includes fusible links for permanently storing the programmed addresses.